cgen: narrow 2-byte deref stores in the wwstage assign arm

The plain `*p = v` arm's storeop map handled 1- and 4-byte pointees
but let a 2-byte one fall to MOVQ, an 8-byte over-store that clobbers
six adjacent bytes (masked in the pinned fixture by the lone frame
slot; loud with `&a[0]` of a [4]i16). cstage fldstoreop maps 2 to
MOVW. Graduates r660_i16_out_param_negative.
This commit is contained in:
2026-08-07 23:48:36 +09:00
parent 83c8a4f34f
commit 58641e97a5
2 changed files with 3 additions and 2 deletions

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@@ -583,7 +583,7 @@ DATABYTEID_EXPECTED_MIN = 911
# When a compiler fix lands the entry fails demanding graduation out of
# this list rather than silently widening coverage. Tracked with the #59
# divergence family.
DATABYTEID_DIVERGED = r660_i16_out_param_negative r71_tagged_return_scratch_mixed \
DATABYTEID_DIVERGED = r71_tagged_return_scratch_mixed \
r76_typeeq_fn_diff_arity r76_typeeq_fn_diff_param_type \
r76_typeeq_fn_io_vtable_shape r76_typeeq_fn_variadic_vs_fixed \
r940_str_forrange_arg r989_libprecond_decodedsize_aligned

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@@ -8955,7 +8955,8 @@ fn cgassign(c: *cgen, n: *syntax.node) void = {
typenodeprimresolved(c, pe, &ps, &uns);
};
if (ps == 1) { storeop = "MOVB"; }
else { if (ps == 4) { storeop = "MOVL"; }; };
else { if (ps == 2) { storeop = "MOVW"; }
else { if (ps == 4) { storeop = "MOVL"; }; }; };
}; }; };
};
// A slice IS the same 3-word {ptr,len,cap}