Hojun-Cho
dc33af6217
The #173 remap loop in cgtryprop gated on the tparam's explicit `!` flag only; a LEGACY union (no marks anywhere) classifies error variants POSITIONALLY (index 0 is success, cstage cg_variant_is_error cgen.c:905) — so wwstage emitted no remap and propagated the callee's raw tag into a differently-ordered caller union, a silent wrong arm (cstage exit 7, wwstage 9 on the banked r700 row). Add the variantiserror twin and gate the loop on it; refresh the drifted cstage cite. Graduates the held e2e row into the corpus (pin 1727/1156/3454) and adds legacy-mode rows to test/lang/tryprop_tag_remap_test.ww: reversed order both directions, slot-0 remap, str payload integrity, a two-hop chain whose pre-fix runtime pass was double-miss tag cancellation (the lang byteid leg pins the emitted remap blocks), and a same-order zero-emission control.