Hojun-Cho
1be0e6b5db
arr[i].field /= %= <<= >>= silently dropped the op (load-combine-store
emitted plain assignment) in BOTH stages — gate-blind, the #133 class.
Route every compound op through the combine dispatch at the indexed-
field arm and hard-error the unhandled operand kinds (float/str/slice/
tagged), per the #133 template (3986818). The runtime-correct target is
the op's own algebra (a OP= b == a = a OP b). Review item #33.
Both stages move in one commit: the fix is a single emission contract —
splitting cstage cgen.c from selfhost cgenexpr.ww would leave the
byte-id gates red between the halves.
374 lines
12 KiB
C
374 lines
12 KiB
C
/*
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* 949_idxfield_compound_run — runtime + byte-id net for #33 (#263 both-
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* stages): a compound assign on an indexed-element FIELD lvalue
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* (`arr[i].field OP= v`) must do a real LOAD-OP-STORE for ALL ten integer
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* ops, not silently no-op the four the arm never wired.
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*
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* Pre-fix: the arr[i].field compound arm (cgenexpr.ww + cgen.c) wired only
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* PLUSEQ/MINUSEQ/STAREQ/AMPEQ/PIPEEQ/CARETEQ; for SLASHEQ/PERCENTEQ/
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* LSHIFTEQ/RSHIFTEQ the old field value loaded into AX, no combine fired,
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* and AX was stored back — a silent no-op in BOTH stages (gate-blind,
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* .s byte-identical). float/str/slice/tagged field compound on this arm
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* was also unguarded (silent fall-through). The fix wires all 10 ops
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* (SLASHEQ/PERCENTEQ via CQO+IDIVQ signed / zero-DX+DIVQ unsigned;
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* LSHIFTEQ via SHLQ; RSHIFTEQ via SARQ signed / SHRQ unsigned) and
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* hard-errors the 4 unwired payload kinds LOUD (rule-7) — mirroring the
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* #133 indexed-scalar + chained-ptr-field arms. cs/ww move together
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* (#263 carve-out); byte-id witnesses rule-10.
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*
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* Each row carries (a) a cstage `ww build` + run asserting the exit code
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* and (b) a w6c vs w6c_ww `.s` cmp (rule-10 byte-id). builderr rows assert
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* BOTH stages fail loud with the cited diagnostic substring.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include <sys/stat.h>
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#include <sys/wait.h>
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static int
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runwait(const char *cmd)
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{
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int rc = system(cmd);
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if (rc == -1) return -1;
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if (WIFEXITED(rc)) return WEXITSTATUS(rc);
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return -1;
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}
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/* builderr + experr: when builderr != 0 the cstage build MUST FAIL and
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* stderr MUST contain experr. wwstage builderr is verified via direct
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* w6c_ww invocation on the same source. Mirrors 945_tuple_nary's pattern
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* for loud-stop verification (rule 7 — never silent). */
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struct row { const char *label; const char *src; int want_exit;
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int builderr; const char *experr; };
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static const struct row rows[] = {
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/* The 6 base ops were already wired; control row that the
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* load-op-store surface is unchanged. 100 + 50 = 150. */
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{ "fld_i32_pluseq",
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"package main;\n"
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"type S = struct { f: i32, g: i32 };\n"
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"export fn main() i32 = {\n"
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" let xs: [2]S = [S{f=100, g=0}, S{f=0, g=0}];\n"
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" xs[0].f += 50;\n"
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" return xs[0].f;\n"
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"};\n", 150, 0, NULL },
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/* i64 field *= : full-width. 6 * 7 = 42. */
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{ "fld_i64_stareq",
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"package main;\n"
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"type S = struct { f: i64, g: i64 };\n"
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"export fn main() i32 = {\n"
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" let xs: [2]S = [S{f=6i64, g=0i64}, S{f=0i64, g=0i64}];\n"
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" xs[0].f *= 7i64;\n"
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" return xs[0].f: i32;\n"
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"};\n", 42, 0, NULL },
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/* #33 newly-wired: signed i32 /= : 100 / 4 = 25. */
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{ "fld_i32_slasheq",
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"package main;\n"
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"type S = struct { f: i32, g: i32 };\n"
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"export fn main() i32 = {\n"
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" let xs: [2]S = [S{f=100, g=0}, S{f=0, g=0}];\n"
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" xs[0].f /= 4;\n"
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" return xs[0].f;\n"
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"};\n", 25, 0, NULL },
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/* signed /= with a NEGATIVE dividend: -17 / 4 = -4 ARITHMETIC
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* (CQO+IDIVQ truncates toward zero); an unsigned DIVQ on the
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* sign-extended -17 yields garbage. This is the row the positive
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* signed /= above cannot tell apart from DIVQ. return (-4+50)=46. */
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{ "fld_i32_slasheq_neg",
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"package main;\n"
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"type S = struct { f: i32, g: i32 };\n"
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"export fn main() i32 = {\n"
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" let xs: [2]S = [S{f=-17, g=0}, S{f=0, g=0}];\n"
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" xs[0].f /= 4;\n"
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" return xs[0].f + 50;\n"
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"};\n", 46, 0, NULL },
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/* unsigned u32 /= : 100u32 / 4u32 = 25 (DIVQ + zero-DX, not IDIVQ). */
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{ "fld_u32_slasheq",
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"package main;\n"
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"type S = struct { f: u32, g: u32 };\n"
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"export fn main() i32 = {\n"
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" let xs: [2]S = [S{f=100u32, g=0u32}, S{f=0u32, g=0u32}];\n"
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" xs[0].f /= 4u32;\n"
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" return xs[0].f: i32;\n"
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"};\n", 25, 0, NULL },
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/* signed i32 %= : 17 % 5 = 2 (result rides DX, MOVQ DX,AX). */
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{ "fld_i32_percenteq",
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"package main;\n"
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"type S = struct { f: i32, g: i32 };\n"
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"export fn main() i32 = {\n"
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" let xs: [2]S = [S{f=17, g=0}, S{f=0, g=0}];\n"
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" xs[0].f %= 5;\n"
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" return xs[0].f;\n"
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"};\n", 2, 0, NULL },
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/* unsigned u32 %= : 100u32 % 7u32 = 2. */
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{ "fld_u32_percenteq",
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"package main;\n"
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"type S = struct { f: u32, g: u32 };\n"
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"export fn main() i32 = {\n"
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" let xs: [2]S = [S{f=100u32, g=0u32}, S{f=0u32, g=0u32}];\n"
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" xs[0].f %= 7u32;\n"
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" return xs[0].f: i32;\n"
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"};\n", 2, 0, NULL },
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/* i32 <<= : 3 << 4 = 48 (SHLQ via CX). */
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{ "fld_i32_lshifteq",
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"package main;\n"
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"type S = struct { f: i32, g: i32 };\n"
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"export fn main() i32 = {\n"
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" let xs: [2]S = [S{f=3, g=0}, S{f=0, g=0}];\n"
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" xs[0].f <<= 4;\n"
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" return xs[0].f;\n"
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"};\n", 48, 0, NULL },
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/* unsigned u32 >>= : 200u32 >> 2 = 50 (SHRQ). */
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{ "fld_u32_rshifteq",
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"package main;\n"
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"type S = struct { f: u32, g: u32 };\n"
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"export fn main() i32 = {\n"
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" let xs: [2]S = [S{f=200u32, g=0u32}, S{f=0u32, g=0u32}];\n"
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" xs[0].f >>= 2u32;\n"
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" return xs[0].f: i32;\n"
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"};\n", 50, 0, NULL },
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/* signed i32 >>= on a NEGATIVE value: -16 >> 2 = -4 ARITHMETIC
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* (SARQ, not SHRQ — a logical shift would give a huge positive).
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* return (-4 + 50) = 46 distinguishes the two. */
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{ "fld_i32_rshifteq_neg",
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"package main;\n"
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"type S = struct { f: i32, g: i32 };\n"
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"export fn main() i32 = {\n"
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" let xs: [2]S = [S{f=-16, g=0}, S{f=0, g=0}];\n"
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" xs[0].f >>= 2;\n"
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" return xs[0].f + 50;\n"
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"};\n", 46, 0, NULL },
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/* via-ptr element (`[N]*S`): the arm derefs once before the field
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* load/store. 10 + 5 = 15. */
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{ "fld_viaptr_pluseq",
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"package main;\n"
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"type S = struct { f: i32, g: i32 };\n"
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"export fn main() i32 = {\n"
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" let a = S{f=10, g=0};\n"
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" let xs: [2]*S = [&a, &a];\n"
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" xs[0].f += 5;\n"
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" return a.f;\n"
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"};\n", 15, 0, NULL },
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/* Plain `arr[i].field = v` control: ASSIGN path byte-id unchanged. */
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{ "fld_plain_assign_ctrl",
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"package main;\n"
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"type S = struct { f: i32, g: i32 };\n"
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"export fn main() i32 = {\n"
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" let xs: [2]S = [S{f=1, g=0}, S{f=0, g=0}];\n"
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" xs[0].f = 99;\n"
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" return xs[0].f;\n"
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"};\n", 99, 0, NULL },
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/* HARD-ERROR rows (#33/rule-7): float/str/slice/tagged FIELD compound
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* builds MUST FAIL LOUD on both stages with the cited diagnostic. */
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{ "fld_he_float",
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"package main;\n"
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"type S = struct { f: f64, g: i32 };\n"
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"export fn main() i32 = {\n"
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" let xs: [2]S = [S{f=1.0, g=0}, S{f=0.0, g=0}];\n"
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" xs[0].f /= 2.0;\n"
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" return 0;\n"
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"};\n", 0, 1, "arr[i].field compound on float field" },
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{ "fld_he_str",
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"package main;\n"
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"type S = struct { f: str, g: i32 };\n"
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"export fn main() i32 = {\n"
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" let xs: [2]S = [S{f=\"a\", g=0}, S{f=\"b\", g=0}];\n"
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" xs[0].f += \"x\";\n"
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" return 0;\n"
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"};\n", 0, 1, "arr[i].field compound on str field" },
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{ "fld_he_slice",
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"package main;\n"
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"type S = struct { f: []u8, g: i32 };\n"
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"export fn main() i32 = {\n"
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" let b: [2]u8 = [1u8, 2u8];\n"
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" let xs: [2]S = [S{f=b[0:2], g=0}, S{f=b[0:2], g=0}];\n"
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" xs[0].f += b[0:1];\n"
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" return 0;\n"
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"};\n", 0, 1, "arr[i].field compound on slice field" },
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{ "fld_he_tagged",
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"package main;\n"
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"type S = struct { f: (i32|str), g: i32 };\n"
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"export fn main() i32 = {\n"
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" let xs: [2]S = [S{f=1, g=0}, S{f=2, g=0}];\n"
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" xs[0].f += 3;\n"
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" return 0;\n"
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"};\n", 0, 1, "arr[i].field compound on tagged field" },
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{ NULL, NULL, 0, 0, NULL }
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};
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static int
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slurp_eq(const char *a, const char *b)
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{
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FILE *fa = fopen(a, "rb");
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FILE *fb = fopen(b, "rb");
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if (!fa || !fb) { if (fa) fclose(fa); if (fb) fclose(fb); return -1; }
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int rc = 0;
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for (;;) {
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int ca = fgetc(fa);
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int cb = fgetc(fb);
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if (ca != cb) { rc = -1; break; }
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if (ca == EOF) break;
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}
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fclose(fa); fclose(fb);
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return rc;
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}
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int
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main(void)
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{
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const char *bin = getenv("BIN");
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if (!bin) bin = "out/bin";
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char absbin[1024];
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if (bin[0] != '/') {
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char cwd[1024];
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if (getcwd(cwd, sizeof cwd) == NULL) return 1;
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snprintf(absbin, sizeof absbin, "%s/%s", cwd, bin);
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bin = absbin;
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}
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char w6c[1100], w6c_ww[1100];
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snprintf(w6c, sizeof w6c, "%s/w6c", bin);
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snprintf(w6c_ww, sizeof w6c_ww, "%s/w6c_ww", bin);
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if (access(w6c_ww, X_OK) != 0) {
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fprintf(stderr, "idxcompound: w6c_ww missing — cannot run the "
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"cs==ww byte-id gate (the whole point of this test)\n");
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return 1;
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}
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int n = 0, fail = 0;
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for (int i = 0; rows[i].src; i++, n++) {
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char src[64];
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snprintf(src, sizeof src, "/tmp/wwidx_%d_%d.ww", getpid(), i);
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FILE *f = fopen(src, "wb");
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if (f == NULL) { fail++; continue; }
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fputs(rows[i].src, f);
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fclose(f);
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/* (a) cstage build + run, OR build-must-fail (builderr rows).
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* For builderr: stderr captured to a temp file; pass iff
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* exit-nonzero AND stderr contains experr substring. */
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char tmpdir[64];
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snprintf(tmpdir, sizeof tmpdir, "/tmp/wwidx_%d_d_%d",
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getpid(), i);
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mkdir(tmpdir, 0755);
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char cmd[2048];
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if (rows[i].builderr) {
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char errf[96];
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snprintf(errf, sizeof errf, "/tmp/wwidx_%d_e_%d",
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getpid(), i);
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snprintf(cmd, sizeof cmd,
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"cd %s && %s/ww build %s >/dev/null 2>%s",
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tmpdir, bin, src, errf);
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int brc = runwait(cmd);
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FILE *ef = fopen(errf, "rb");
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char ebuf[4096];
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size_t en = 0;
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if (ef) { en = fread(ebuf, 1, sizeof ebuf - 1, ef);
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fclose(ef); }
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ebuf[en] = '\0';
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int ok = (brc != 0)
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&& (rows[i].experr == NULL
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|| strstr(ebuf, rows[i].experr) != NULL);
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if (!ok) {
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fprintf(stderr, "row[%s]: cstage expected "
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"builderr+'%s' (brc=%d, stderr='%s')\n",
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rows[i].label,
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rows[i].experr ? rows[i].experr : "(any)",
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brc, ebuf);
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fail++;
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}
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/* Also verify wwstage hard-errors with the SAME message
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* (rule-10 — both stages identical diagnostic). Invoke
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* w6c_ww directly on the .ww source. */
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snprintf(cmd, sizeof cmd,
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"%s -o /dev/null %s >/dev/null 2>%s",
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w6c_ww, src, errf);
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int wrc = runwait(cmd);
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ef = fopen(errf, "rb"); en = 0;
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if (ef) { en = fread(ebuf, 1, sizeof ebuf - 1, ef);
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fclose(ef); }
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ebuf[en] = '\0';
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int wok = (wrc != 0)
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&& (rows[i].experr == NULL
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|| strstr(ebuf, rows[i].experr) != NULL);
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if (!wok) {
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fprintf(stderr, "row[%s]: wwstage expected "
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"builderr+'%s' (wrc=%d, stderr='%s')\n",
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rows[i].label,
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rows[i].experr ? rows[i].experr : "(any)",
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wrc, ebuf);
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fail++;
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}
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unlink(errf);
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unlink(src); rmdir(tmpdir);
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continue;
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}
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snprintf(cmd, sizeof cmd, "cd %s && %s/ww build %s",
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tmpdir, bin, src);
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if (runwait(cmd) != 0) {
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fprintf(stderr, "row[%s]: cstage build failed\n",
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rows[i].label);
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fail++;
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unlink(src); rmdir(tmpdir);
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continue;
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}
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char outbin[128];
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const char *base = strrchr(src, '/');
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base = base ? base + 1 : src;
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snprintf(outbin, sizeof outbin, "%s/%s", tmpdir, base);
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char *dot = strrchr(outbin, '.');
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if (dot && strcmp(dot, ".ww") == 0) *dot = '\0';
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int got = runwait(outbin);
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if (got != rows[i].want_exit) {
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fprintf(stderr, "row[%s]: cstage exit %d, want %d\n",
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rows[i].label, got, rows[i].want_exit);
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fail++;
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}
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unlink(outbin); rmdir(tmpdir);
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/* (b) cs==ww byte-id gate. */
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char cs_s[64], ws_s[64];
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snprintf(cs_s, sizeof cs_s, "/tmp/wwidx_%d_%d_cs.s",
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getpid(), i);
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snprintf(ws_s, sizeof ws_s, "/tmp/wwidx_%d_%d_ww.s",
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getpid(), i);
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snprintf(cmd, sizeof cmd, "%s -o %s %s 2>/dev/null",
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w6c, cs_s, src);
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if (runwait(cmd) != 0) {
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fprintf(stderr, "row[%s]: w6c failed\n", rows[i].label);
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fail++; unlink(src); continue;
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}
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snprintf(cmd, sizeof cmd, "%s -o %s %s 2>/dev/null",
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w6c_ww, ws_s, src);
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if (runwait(cmd) != 0) {
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fprintf(stderr, "row[%s]: w6c_ww failed\n",
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rows[i].label);
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fail++; unlink(src); unlink(cs_s); continue;
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}
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if (slurp_eq(cs_s, ws_s) != 0) {
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fprintf(stderr,
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"row[%s]: cstage/wwstage .s DIFFER (rule-10 "
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"byte-id violation)\n", rows[i].label);
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fail++;
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}
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unlink(src); unlink(cs_s); unlink(ws_s);
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}
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if (fail) {
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fprintf(stderr, "%d/%d idxfield-compound tests failed\n",
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fail, n);
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return 1;
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}
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printf("idxfield-compound: %d/%d ok (cstage run + cs==ww byte-id)\n",
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n, n);
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return 0;
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}
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