/*
 * 949_idxfield_compound_run — runtime + byte-id net for #33 (#263 both-
 * stages): a compound assign on an indexed-element FIELD lvalue
 * (`arr[i].field OP= v`) must do a real LOAD-OP-STORE for ALL ten integer
 * ops, not silently no-op the four the arm never wired.
 *
 * Pre-fix: the arr[i].field compound arm (cgenexpr.ww + cgen.c) wired only
 * PLUSEQ/MINUSEQ/STAREQ/AMPEQ/PIPEEQ/CARETEQ; for SLASHEQ/PERCENTEQ/
 * LSHIFTEQ/RSHIFTEQ the old field value loaded into AX, no combine fired,
 * and AX was stored back — a silent no-op in BOTH stages (gate-blind,
 * .s byte-identical). float/str/slice/tagged field compound on this arm
 * was also unguarded (silent fall-through). The fix wires all 10 ops
 * (SLASHEQ/PERCENTEQ via CQO+IDIVQ signed / zero-DX+DIVQ unsigned;
 * LSHIFTEQ via SHLQ; RSHIFTEQ via SARQ signed / SHRQ unsigned) and
 * hard-errors the 4 unwired payload kinds LOUD (rule-7) — mirroring the
 * #133 indexed-scalar + chained-ptr-field arms. cs/ww move together
 * (#263 carve-out); byte-id witnesses rule-10.
 *
 * Each row carries (a) a cstage `ww build` + run asserting the exit code
 * and (b) a w6c vs w6c_ww `.s` cmp (rule-10 byte-id). builderr rows assert
 * BOTH stages fail loud with the cited diagnostic substring.
 */
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <sys/stat.h>
#include <sys/wait.h>

static int
runwait(const char *cmd)
{
	int rc = system(cmd);
	if (rc == -1) return -1;
	if (WIFEXITED(rc)) return WEXITSTATUS(rc);
	return -1;
}

/* builderr + experr: when builderr != 0 the cstage build MUST FAIL and
 * stderr MUST contain experr. wwstage builderr is verified via direct
 * w6c_ww invocation on the same source. Mirrors 945_tuple_nary's pattern
 * for loud-stop verification (rule 7 — never silent). */
struct row { const char *label; const char *src; int want_exit;
             int builderr; const char *experr; };

static const struct row rows[] = {
	/* The 6 base ops were already wired; control row that the
	 * load-op-store surface is unchanged. 100 + 50 = 150. */
	{ "fld_i32_pluseq",
	  "package main;\n"
	  "type S = struct { f: i32, g: i32 };\n"
	  "export fn main() i32 = {\n"
	  "	let xs: [2]S = [S{f=100, g=0}, S{f=0, g=0}];\n"
	  "	xs[0].f += 50;\n"
	  "	return xs[0].f;\n"
	  "};\n", 150, 0, NULL },
	/* i64 field *= : full-width. 6 * 7 = 42. */
	{ "fld_i64_stareq",
	  "package main;\n"
	  "type S = struct { f: i64, g: i64 };\n"
	  "export fn main() i32 = {\n"
	  "	let xs: [2]S = [S{f=6i64, g=0i64}, S{f=0i64, g=0i64}];\n"
	  "	xs[0].f *= 7i64;\n"
	  "	return xs[0].f: i32;\n"
	  "};\n", 42, 0, NULL },
	/* #33 newly-wired: signed i32 /= : 100 / 4 = 25. */
	{ "fld_i32_slasheq",
	  "package main;\n"
	  "type S = struct { f: i32, g: i32 };\n"
	  "export fn main() i32 = {\n"
	  "	let xs: [2]S = [S{f=100, g=0}, S{f=0, g=0}];\n"
	  "	xs[0].f /= 4;\n"
	  "	return xs[0].f;\n"
	  "};\n", 25, 0, NULL },
	/* signed /= with a NEGATIVE dividend: -17 / 4 = -4 ARITHMETIC
	 * (CQO+IDIVQ truncates toward zero); an unsigned DIVQ on the
	 * sign-extended -17 yields garbage. This is the row the positive
	 * signed /= above cannot tell apart from DIVQ. return (-4+50)=46. */
	{ "fld_i32_slasheq_neg",
	  "package main;\n"
	  "type S = struct { f: i32, g: i32 };\n"
	  "export fn main() i32 = {\n"
	  "	let xs: [2]S = [S{f=-17, g=0}, S{f=0, g=0}];\n"
	  "	xs[0].f /= 4;\n"
	  "	return xs[0].f + 50;\n"
	  "};\n", 46, 0, NULL },
	/* unsigned u32 /= : 100u32 / 4u32 = 25 (DIVQ + zero-DX, not IDIVQ). */
	{ "fld_u32_slasheq",
	  "package main;\n"
	  "type S = struct { f: u32, g: u32 };\n"
	  "export fn main() i32 = {\n"
	  "	let xs: [2]S = [S{f=100u32, g=0u32}, S{f=0u32, g=0u32}];\n"
	  "	xs[0].f /= 4u32;\n"
	  "	return xs[0].f: i32;\n"
	  "};\n", 25, 0, NULL },
	/* signed i32 %= : 17 % 5 = 2 (result rides DX, MOVQ DX,AX). */
	{ "fld_i32_percenteq",
	  "package main;\n"
	  "type S = struct { f: i32, g: i32 };\n"
	  "export fn main() i32 = {\n"
	  "	let xs: [2]S = [S{f=17, g=0}, S{f=0, g=0}];\n"
	  "	xs[0].f %= 5;\n"
	  "	return xs[0].f;\n"
	  "};\n", 2, 0, NULL },
	/* unsigned u32 %= : 100u32 % 7u32 = 2. */
	{ "fld_u32_percenteq",
	  "package main;\n"
	  "type S = struct { f: u32, g: u32 };\n"
	  "export fn main() i32 = {\n"
	  "	let xs: [2]S = [S{f=100u32, g=0u32}, S{f=0u32, g=0u32}];\n"
	  "	xs[0].f %= 7u32;\n"
	  "	return xs[0].f: i32;\n"
	  "};\n", 2, 0, NULL },
	/* i32 <<= : 3 << 4 = 48 (SHLQ via CX). */
	{ "fld_i32_lshifteq",
	  "package main;\n"
	  "type S = struct { f: i32, g: i32 };\n"
	  "export fn main() i32 = {\n"
	  "	let xs: [2]S = [S{f=3, g=0}, S{f=0, g=0}];\n"
	  "	xs[0].f <<= 4;\n"
	  "	return xs[0].f;\n"
	  "};\n", 48, 0, NULL },
	/* unsigned u32 >>= : 200u32 >> 2 = 50 (SHRQ). */
	{ "fld_u32_rshifteq",
	  "package main;\n"
	  "type S = struct { f: u32, g: u32 };\n"
	  "export fn main() i32 = {\n"
	  "	let xs: [2]S = [S{f=200u32, g=0u32}, S{f=0u32, g=0u32}];\n"
	  "	xs[0].f >>= 2u32;\n"
	  "	return xs[0].f: i32;\n"
	  "};\n", 50, 0, NULL },
	/* signed i32 >>= on a NEGATIVE value: -16 >> 2 = -4 ARITHMETIC
	 * (SARQ, not SHRQ — a logical shift would give a huge positive).
	 * return (-4 + 50) = 46 distinguishes the two. */
	{ "fld_i32_rshifteq_neg",
	  "package main;\n"
	  "type S = struct { f: i32, g: i32 };\n"
	  "export fn main() i32 = {\n"
	  "	let xs: [2]S = [S{f=-16, g=0}, S{f=0, g=0}];\n"
	  "	xs[0].f >>= 2;\n"
	  "	return xs[0].f + 50;\n"
	  "};\n", 46, 0, NULL },
	/* via-ptr element (`[N]*S`): the arm derefs once before the field
	 * load/store. 10 + 5 = 15. */
	{ "fld_viaptr_pluseq",
	  "package main;\n"
	  "type S = struct { f: i32, g: i32 };\n"
	  "export fn main() i32 = {\n"
	  "	let a = S{f=10, g=0};\n"
	  "	let xs: [2]*S = [&a, &a];\n"
	  "	xs[0].f += 5;\n"
	  "	return a.f;\n"
	  "};\n", 15, 0, NULL },
	/* Plain `arr[i].field = v` control: ASSIGN path byte-id unchanged. */
	{ "fld_plain_assign_ctrl",
	  "package main;\n"
	  "type S = struct { f: i32, g: i32 };\n"
	  "export fn main() i32 = {\n"
	  "	let xs: [2]S = [S{f=1, g=0}, S{f=0, g=0}];\n"
	  "	xs[0].f = 99;\n"
	  "	return xs[0].f;\n"
	  "};\n", 99, 0, NULL },
	/* HARD-ERROR rows (#33/rule-7): float/str/slice/tagged FIELD compound
	 * builds MUST FAIL LOUD on both stages with the cited diagnostic. */
	{ "fld_he_float",
	  "package main;\n"
	  "type S = struct { f: f64, g: i32 };\n"
	  "export fn main() i32 = {\n"
	  "	let xs: [2]S = [S{f=1.0, g=0}, S{f=0.0, g=0}];\n"
	  "	xs[0].f /= 2.0;\n"
	  "	return 0;\n"
	  "};\n", 0, 1, "arr[i].field compound on float field" },
	{ "fld_he_str",
	  "package main;\n"
	  "type S = struct { f: str, g: i32 };\n"
	  "export fn main() i32 = {\n"
	  "	let xs: [2]S = [S{f=\"a\", g=0}, S{f=\"b\", g=0}];\n"
	  "	xs[0].f += \"x\";\n"
	  "	return 0;\n"
	  "};\n", 0, 1, "arr[i].field compound on str field" },
	{ "fld_he_slice",
	  "package main;\n"
	  "type S = struct { f: []u8, g: i32 };\n"
	  "export fn main() i32 = {\n"
	  "	let b: [2]u8 = [1u8, 2u8];\n"
	  "	let xs: [2]S = [S{f=b[0:2], g=0}, S{f=b[0:2], g=0}];\n"
	  "	xs[0].f += b[0:1];\n"
	  "	return 0;\n"
	  "};\n", 0, 1, "arr[i].field compound on slice field" },
	{ "fld_he_tagged",
	  "package main;\n"
	  "type S = struct { f: (i32|str), g: i32 };\n"
	  "export fn main() i32 = {\n"
	  "	let xs: [2]S = [S{f=1, g=0}, S{f=2, g=0}];\n"
	  "	xs[0].f += 3;\n"
	  "	return 0;\n"
	  "};\n", 0, 1, "arr[i].field compound on tagged field" },
	{ NULL, NULL, 0, 0, NULL }
};

static int
slurp_eq(const char *a, const char *b)
{
	FILE *fa = fopen(a, "rb");
	FILE *fb = fopen(b, "rb");
	if (!fa || !fb) { if (fa) fclose(fa); if (fb) fclose(fb); return -1; }
	int rc = 0;
	for (;;) {
		int ca = fgetc(fa);
		int cb = fgetc(fb);
		if (ca != cb) { rc = -1; break; }
		if (ca == EOF) break;
	}
	fclose(fa); fclose(fb);
	return rc;
}

int
main(void)
{
	const char *bin = getenv("BIN");
	if (!bin) bin = "out/bin";
	char absbin[1024];
	if (bin[0] != '/') {
		char cwd[1024];
		if (getcwd(cwd, sizeof cwd) == NULL) return 1;
		snprintf(absbin, sizeof absbin, "%s/%s", cwd, bin);
		bin = absbin;
	}

	char w6c[1100], w6c_ww[1100];
	snprintf(w6c, sizeof w6c, "%s/w6c", bin);
	snprintf(w6c_ww, sizeof w6c_ww, "%s/w6c_ww", bin);
	if (access(w6c_ww, X_OK) != 0) {
		fprintf(stderr, "idxcompound: w6c_ww missing — cannot run the "
		    "cs==ww byte-id gate (the whole point of this test)\n");
		return 1;
	}

	int n = 0, fail = 0;
	for (int i = 0; rows[i].src; i++, n++) {
		char src[64];
		snprintf(src, sizeof src, "/tmp/wwidx_%d_%d.ww", getpid(), i);
		FILE *f = fopen(src, "wb");
		if (f == NULL) { fail++; continue; }
		fputs(rows[i].src, f);
		fclose(f);

		/* (a) cstage build + run, OR build-must-fail (builderr rows).
		 * For builderr: stderr captured to a temp file; pass iff
		 * exit-nonzero AND stderr contains experr substring. */
		char tmpdir[64];
		snprintf(tmpdir, sizeof tmpdir, "/tmp/wwidx_%d_d_%d",
		    getpid(), i);
		mkdir(tmpdir, 0755);

		char cmd[2048];
		if (rows[i].builderr) {
			char errf[96];
			snprintf(errf, sizeof errf, "/tmp/wwidx_%d_e_%d",
			    getpid(), i);
			snprintf(cmd, sizeof cmd,
			    "cd %s && %s/ww build %s >/dev/null 2>%s",
			    tmpdir, bin, src, errf);
			int brc = runwait(cmd);
			FILE *ef = fopen(errf, "rb");
			char ebuf[4096];
			size_t en = 0;
			if (ef) { en = fread(ebuf, 1, sizeof ebuf - 1, ef);
			    fclose(ef); }
			ebuf[en] = '\0';
			int ok = (brc != 0)
			    && (rows[i].experr == NULL
			        || strstr(ebuf, rows[i].experr) != NULL);
			if (!ok) {
				fprintf(stderr, "row[%s]: cstage expected "
				    "builderr+'%s' (brc=%d, stderr='%s')\n",
				    rows[i].label,
				    rows[i].experr ? rows[i].experr : "(any)",
				    brc, ebuf);
				fail++;
			}

			/* Also verify wwstage hard-errors with the SAME message
			 * (rule-10 — both stages identical diagnostic). Invoke
			 * w6c_ww directly on the .ww source. */
			snprintf(cmd, sizeof cmd,
			    "%s -o /dev/null %s >/dev/null 2>%s",
			    w6c_ww, src, errf);
			int wrc = runwait(cmd);
			ef = fopen(errf, "rb"); en = 0;
			if (ef) { en = fread(ebuf, 1, sizeof ebuf - 1, ef);
			    fclose(ef); }
			ebuf[en] = '\0';
			int wok = (wrc != 0)
			    && (rows[i].experr == NULL
			        || strstr(ebuf, rows[i].experr) != NULL);
			if (!wok) {
				fprintf(stderr, "row[%s]: wwstage expected "
				    "builderr+'%s' (wrc=%d, stderr='%s')\n",
				    rows[i].label,
				    rows[i].experr ? rows[i].experr : "(any)",
				    wrc, ebuf);
				fail++;
			}
			unlink(errf);
			unlink(src); rmdir(tmpdir);
			continue;
		}

		snprintf(cmd, sizeof cmd, "cd %s && %s/ww build %s",
		    tmpdir, bin, src);
		if (runwait(cmd) != 0) {
			fprintf(stderr, "row[%s]: cstage build failed\n",
			    rows[i].label);
			fail++;
			unlink(src); rmdir(tmpdir);
			continue;
		}

		char outbin[128];
		const char *base = strrchr(src, '/');
		base = base ? base + 1 : src;
		snprintf(outbin, sizeof outbin, "%s/%s", tmpdir, base);
		char *dot = strrchr(outbin, '.');
		if (dot && strcmp(dot, ".ww") == 0) *dot = '\0';

		int got = runwait(outbin);
		if (got != rows[i].want_exit) {
			fprintf(stderr, "row[%s]: cstage exit %d, want %d\n",
			    rows[i].label, got, rows[i].want_exit);
			fail++;
		}
		unlink(outbin); rmdir(tmpdir);

		/* (b) cs==ww byte-id gate. */
		char cs_s[64], ws_s[64];
		snprintf(cs_s, sizeof cs_s, "/tmp/wwidx_%d_%d_cs.s",
		    getpid(), i);
		snprintf(ws_s, sizeof ws_s, "/tmp/wwidx_%d_%d_ww.s",
		    getpid(), i);

		snprintf(cmd, sizeof cmd, "%s -o %s %s 2>/dev/null",
		    w6c, cs_s, src);
		if (runwait(cmd) != 0) {
			fprintf(stderr, "row[%s]: w6c failed\n", rows[i].label);
			fail++; unlink(src); continue;
		}
		snprintf(cmd, sizeof cmd, "%s -o %s %s 2>/dev/null",
		    w6c_ww, ws_s, src);
		if (runwait(cmd) != 0) {
			fprintf(stderr, "row[%s]: w6c_ww failed\n",
			    rows[i].label);
			fail++; unlink(src); unlink(cs_s); continue;
		}
		if (slurp_eq(cs_s, ws_s) != 0) {
			fprintf(stderr,
			    "row[%s]: cstage/wwstage .s DIFFER (rule-10 "
			    "byte-id violation)\n", rows[i].label);
			fail++;
		}
		unlink(src); unlink(cs_s); unlink(ws_s);
	}

	if (fail) {
		fprintf(stderr, "%d/%d idxfield-compound tests failed\n",
		    fail, n);
		return 1;
	}
	printf("idxfield-compound: %d/%d ok (cstage run + cs==ww byte-id)\n",
	    n, n);
	return 0;
}