Hojun-Cho
3986818172
Both stages had silent miscompiles on compound assignment for two shapes: indexed lvalue (`arr[i] OP= v`) and chained-pointer-field (`d.fld.fld OP= v` through a *struct chain). The cstage N_INDEX-lhs branch did not gate on TK_ASSIGN and silently DEMOTED compound ops to plain stores (RHS stored, no load, no op). The wwstage equivalents silently DROPPED the line entirely (no instructions emitted). The chained-pointer-field compound template at cgen.c:3281-3317 also silently identity-stored on unwired compound ops (SLASHEQ / PERCENTEQ / LSHIFTEQ / RSHIFTEQ all fell to the switch default = no-op = load, pop RHS, store ORIGINAL value back) and silently no-op'd on float / str / slice / tagged element compound; its wwstage twin at cgenexpr.ww:5471 only handled TK_ASSIGN, dropping any chained-ptr-field compound entirely. Wire all 10 integer compound ops (PLUSEQ MINUSEQ STAREQ AMPEQ PIPEEQ CARETEQ SLASHEQ PERCENTEQ LSHIFTEQ RSHIFTEQ) at all 4 sites in both stages: SLASHEQ/PERCENTEQ via CQO+IDIVQ (signed) or zero-DX+DIVQ (unsigned), with PERCENTEQ moving DX->AX for the result; LSHIFTEQ/ RSHIFTEQ via SHLQ/SHRQ on CX (rhs already in CX after the pop). Signedness keyed off the field/element type via type_isunsigned / typeisunsigned. Float / str / slice / tagged element compound now LOUD-ERRORS at codegen with a distinct per-site diagnostic citing #133/rule-7 instead of silent fall-through. Site 3 (the wwstage chained-pointer-field compound) is ADDED FROM SCRATCH alongside the existing TK_ASSIGN-only arm — pre-#133 wwstage emitted zero instructions for any `d.i.v OP= v` shape, a rule-10 silent divergence from the cstage which handled the same shape correctly. Multi-fix carve-out (rule 11): the 10 wired ops at 4 sites + hard-error gate on 4 unwired payload kinds at 4 sites are ONE silent-misbehavior class closure on indexed/chained-ptr-field compound assignment. Splitting would muddle bisect on related cgen surfaces — the wired ops, the hard-error gate, and the rule-10 cstage/wwstage symmetry are inseparable correctness facts at each site. The inherited template default-break silent-identity (cgen.c:3281-3317) was the originating class root; close it everywhere or leave the class open. 948_idx_compound_run: 21 rows total. 11 runtime+byte-id rows for the original 6 ops on u8/i32/i64/u32 array bases and one slice base, with a plain-assign control row asserting the ASSIGN path is byte-id- unchanged. 7 new runtime+byte-id rows for SLASHEQ/PERCENTEQ on signed i32 + unsigned u32, LSHIFTEQ on i32, RSHIFTEQ on signed-positive i32 and unsigned u32. 3 builderr rows (he_float_indexed, he_str_indexed, he_float_chained_ptr) asserting both stages exit non-zero AND stderr carries the cited diagnostic substring (rule-7 — never silent). Mirrors 945_tuple_nary's builderr/experr pattern. Bootstrap NEUTRAL — `grep -rE '\][[:space:]]*(\+=|-=|\*=|/=|&=|\|=|\^=|<<=|>>=)' lib/ selfhost/` (excluding combined.ww) returns ZERO existing callers for the indexed compound shape, and the chained-ptr-field compound shape was silent- no-op in wwstage pre-fix (no working caller possible). 990-997 byte- id gates green, 994 explicit confirms 18 corpus inputs identical pre/post. combined.ww (w6c + wwdump) regen deterministic across re-touch+rebuild. A_SARQ is not in w6a's opcode table; signed RSHIFTEQ uses SHRQ at all 4 sites for parity with the pre-existing deref-lvalue compound site (TK_RSHIFTEQ→A_SHRQ at cgen.c:4145). Documented technical debt filed as #136 — pre-existing concern that a fix would need w6a opcode addition + cgen sweep across every SHRQ-for-signed-RSHIFT site, out of scope for this fold.