Hojun-Cho
166431a2da
cgreturn's variant-widen arm only filled the registers each variant's payload needed: scalar variants left CX and R8 stale; str variant left R8 stale. The receiver (cg_widen_tagged_store non-N_IDENT branch) writes all four ABI words to the dst slot unconditionally, so caller-side residue in CX/R8 (the array-index IMULQ being the canonical primer) landed at slot+16 and slot+24. Worker-fmtparser surfaced this through fprintf's loop body where array indexing primed CX and a 24B-return helper failed to clear it; bug isn't loop-specific — straight-line repro at /tmp/wcrs_repro/ repro8.ww confirms. Patch: emit `MOVQ $0, CX` after the variant's register shuffle when the slot exceeds 16B and the variant doesn't fill CX; same for R8 when the slot exceeds 24B. Symmetric across cstage cgen.c and wwstage cgenstmt.ww. Order: zero-MOVQs precede `MOVQ $tag, AX` so AX-as-staging stays safe. Inline comment at cg_widen_tagged_store non-N_IDENT branch documents the producer-zero contract. Test 707 (cgreturn_variant_zero): 6 rows × both stages = 12 fixtures. Covers scalar/bool/str returns after array-index priming in straight-line / single-loop body / nested-loop body / mixed-variant loop. Asm byte-identity check intentionally omitted; wwstage taggedvariantindex divergence on str/bool N_IDENT is filed as task #20. 995_self_rebuild covers the broader cross-stage drift surface. ww2 == ww3 == ww4 byte-identical post-fix. 67/67 green. Deferred (followups filed): #20 wwstage taggedvariantindex, #21 [N]str/[N]bool array-literal non-pointer-half writes, #22 consolidate variant-widen into uniform scratch-slot path.