cstage+selfhost+test: cgreturn TY_STRUCT <=24B via AX/DX/CX

Whole-struct return ABI for sizes <=24B. Both stages materialise rhs
into a zero-padded 24B @retscr scratch slot, then load AX=bytes[0..7],
DX=bytes[8..15], CX=bytes[16..23] unconditionally — three MOVQs
regardless of declared struct size, so the receive side (landing in
task #5) can read all three words and mask by the declared size. R8
stays reserved for the tagged-return 4th word; the uniform-MOVQ shape
is cheap over a size-conditional partial-load and keeps the producer
diff vs the existing tagged-return AX/DX/CX/R8 path minimal.

Two rhs shapes wired this pass: N_IDENT (word-copy from rhs local slot,
MOVQ pairs + MOVL/MOVB tail bounded by declared struct size) and
N_STRUCTLIT (field-walk; tagged fields delegate to the existing tagged
widening helper, float fields go through X0, int fields use MOVQ/MOVL/
MOVB by field size). Sizes >24B fall through to the existing scalar
path (only AX gets the first qword), pending sret in a future task.
N_CALL chain-return (`return otherfn()`) is deferred to task #5's
receive side — until that lands the call-result lives in caller regs.

The wwstage mirror in cgenstmt.ww matches cgen.c byte-for-byte on the
new branch; cgendecl.ww's scanlocals pre-reserves 24B for @retscr under
the same predicate (N_RETURN, fnret is N_TNAME, structlookup hit,
totsize<=24, rhs is N_IDENT|N_STRUCTLIT) since wwstage writes its
prologue SUBQ from the upfront frame total — cstage patches SUBQ at fn
end so it can allocate inline.

Latent fsz==2 MOVW divergence between stages (cstage structlit int-
branch only special-cases fsz 1/4, wwstage's fieldstoreop also returns
MOVW for fsz==2) tracked as task #13; not exercised by the new fixtures
or by any current selfhost <=24B struct return.

main.combined.ww files also pick up worker-checkfix's wwstage
architectural comment from 7f60ebb (auto-regen ran after that commit).
This commit is contained in:
2026-05-15 15:19:38 +09:00
parent 1d5ff201ee
commit aee8149754
7 changed files with 937 additions and 0 deletions

View File

@@ -0,0 +1,256 @@
/*
* 698_cgreturn_struct — whole-struct return ABI for sizes <= 24B.
*
* Pre-#7: `return s;` from a struct-returning fn fell through to the
* scalar path: only the first 8 bytes of the struct made it to AX,
* the rest was silently dropped. Compounded with the receive side
* (#5 N_ASSIGN whole-STRUCT rhs) being unwired, struct returns were
* a no-op end-to-end.
*
* #7 wires the producer side: cgreturn now materialises the struct
* into a zero-padded 24B scratch slot (`@retscr`), then loads
* AX/DX/CX from the slot unconditionally — three MOVQs regardless of
* declared size — so receiver code (landing in #5) can read all
* three words and mask by the declared struct size. R8 stays
* reserved for the tagged-return 4th word; sret for sizes > 24B is
* a separate future task.
*
* What this test pins:
* - cstage and wwstage emit byte-identical asm for every fixture
* (the bootstrap byte-identity invariant — if either stage's
* scanlocals / cgreturn drifts, the diff catches it).
* - Each fixture compiles+links+runs without crashing under both
* drivers (proves the prologue SUBQ reserves enough frame for
* the @retscr scratch; an under-booked frame would smash the
* saved BP / return address on the load-back).
* - End-to-end value verification (caller reads AX/DX/CX into a
* dst slot) is deferred to #5's test surface, since that's the
* receive side. Until then the call's result is discarded and
* main returns a literal exit code; we're checking the cgreturn
* side doesn't crash or produce invalid asm.
*
* Coverage: five struct shapes — 8B one-field, 16B two-i64, 24B
* three-i64 (the headline ABI shape), mixed-alignment i32+i32+i64+i64
* (totsize 24 with the i32-pair packed), and N_IDENT rhs (let-init
* then `return p;`) vs N_STRUCTLIT rhs (`return T{...};`). The
* 25B+ sret case is explicitly OUT OF SCOPE — falls through to the
* existing scalar path (only AX gets the first qword); not pinned
* here.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <sys/stat.h>
#include <sys/wait.h>
static int
runwait(const char *cmd)
{
int rc = system(cmd);
if (rc == -1) return -1;
if (WIFEXITED(rc)) return WEXITSTATUS(rc);
return -1;
}
struct row { const char *label; const char *src; int want; };
static const struct row rows[] = {
/* 8B single-i64 field: smallest struct return. Exercises the
* sz=8 path where only AX is meaningful (DX/CX zero-padded). */
{ "one_i64_lit",
"type one = struct { v: i64 };\n"
"fn mk() one = { return one { v = 42i64 }; };\n"
"fn main() i32 = { mk(); return 0; };\n",
0 },
/* 16B two-i64 (the SysV 16B aggregate shape, but routed through
* our 3-reg path uniformly). N_STRUCTLIT rhs. */
{ "pair_i64_lit",
"type pair = struct { a: i64, b: i64 };\n"
"fn mk() pair = { return pair { a = 1i64, b = 2i64 }; };\n"
"fn main() i32 = { mk(); return 0; };\n",
0 },
/* 24B three-i64 — the headline shape: AX/DX/CX each carry one
* word, no zero pad needed in scratch. */
{ "trip_i64_lit",
"type trip = struct { x: i64, y: i64, z: i64 };\n"
"fn mk() trip = { return trip { x = 7i64, y = 11i64, z = 13i64 }; };\n"
"fn main() i32 = { mk(); return 0; };\n",
0 },
/* Mixed i32+i32+i64+i64: registerstruct packs two i32s into
* one quadword (a@0, b@4, c@8, d@16), totsize 24 after tail
* pad. Exercises the MOVL store-op branch in the structlit
* field walker. */
{ "mix_i32_i32_i64_i64_lit",
"type mix = struct { a: i32, b: i32, c: i64, d: i64 };\n"
"fn mk() mix = { return mix { a = 3, b = 5, c = 11i64, d = 12i64 }; };\n"
"fn main() i32 = { mk(); return 0; };\n",
0 },
/* N_IDENT rhs: let-init the struct then return it. Exercises
* the word-copy-from-slot branch (vs the structlit branch
* above). The let-init zero-fills the slot, so the trailing
* partial-word handlers (MOVL/MOVB) stay dormant — but the
* sz=24 path covers all three MOVQ words. */
{ "trip_i64_ident",
"type trip = struct { x: i64, y: i64, z: i64 };\n"
"fn mk() trip = {\n"
" let p: trip = trip { x = 100i64, y = 200i64, z = 300i64 };\n"
" return p;\n"
"};\n"
"fn main() i32 = { mk(); return 0; };\n",
0 },
};
static int
run_driver(const char *driver, const struct row *r, int i)
{
char src[64], tmpdir[64], cmd[1024];
snprintf(src, sizeof src, "/tmp/wcrs_%d_%d.ww", getpid(), i);
snprintf(tmpdir, sizeof tmpdir, "/tmp/wcrs_%d_d_%d", getpid(), i);
FILE *f = fopen(src, "wb");
if (!f) return -1;
fputs(r->src, f);
fclose(f);
mkdir(tmpdir, 0755);
snprintf(cmd, sizeof cmd, "cd %s && %s build %s",
tmpdir, driver, src);
if (runwait(cmd) != 0) {
fprintf(stderr, "row[%s]: build via %s failed\n",
r->label, driver);
unlink(src); rmdir(tmpdir);
return -1;
}
const char *base = strrchr(src, '/');
base = base ? base + 1 : src;
char outbin[128];
snprintf(outbin, sizeof outbin, "%s/%s", tmpdir, base);
char *dot = strrchr(outbin, '.');
if (dot && strcmp(dot, ".ww") == 0) *dot = '\0';
int got = runwait(outbin);
unlink(src); unlink(outbin); rmdir(tmpdir);
return got;
}
/* asm_byte_identical — generate .s via cstage's w6c and wwstage's w6c_ww
* and diff. Catches scanlocals / cgreturn drift between the two stages,
* which the bootstrap byte-identity (995_self_rebuild) covers globally
* but doesn't surface as a focused-fixture failure. */
static int
asm_byte_identical(const char *bin, const struct row *r, int i)
{
char src[64], cs[64], ws[64], cmd[1024];
snprintf(src, sizeof src, "/tmp/wcrs_asm_%d_%d.ww", getpid(), i);
snprintf(cs, sizeof cs, "/tmp/wcrs_asm_%d_%d_c.s", getpid(), i);
snprintf(ws, sizeof ws, "/tmp/wcrs_asm_%d_%d_w.s", getpid(), i);
FILE *f = fopen(src, "wb");
if (!f) return -1;
fputs(r->src, f);
fclose(f);
snprintf(cmd, sizeof cmd, "%s/w6c -o %s %s 2>/dev/null", bin, cs, src);
if (runwait(cmd) != 0) {
fprintf(stderr, "row[%s]: w6c errored\n", r->label);
unlink(src);
return -1;
}
snprintf(cmd, sizeof cmd, "%s/w6c_ww -o %s %s 2>/dev/null",
bin, ws, src);
if (runwait(cmd) != 0) {
fprintf(stderr, "row[%s]: w6c_ww errored\n", r->label);
unlink(src); unlink(cs);
return -1;
}
FILE *fc = fopen(cs, "rb");
FILE *fw = fopen(ws, "rb");
int rc = 0;
if (!fc || !fw) {
rc = -1;
} else {
for (;;) {
int a = fgetc(fc);
int b = fgetc(fw);
if (a != b) { rc = -1; break; }
if (a == EOF) break;
}
}
if (fc) fclose(fc);
if (fw) fclose(fw);
if (rc != 0)
fprintf(stderr, "row[%s]: cstage vs wwstage asm differs\n",
r->label);
unlink(src); unlink(cs); unlink(ws);
return rc;
}
int
main(void)
{
const char *bin = getenv("BIN");
if (!bin) bin = "out/bin";
char absbin[1024];
if (bin[0] != '/') {
char cwd[1024];
if (getcwd(cwd, sizeof cwd) == NULL) return 1;
snprintf(absbin, sizeof absbin, "%s/%s", cwd, bin);
bin = absbin;
}
char cdrv[1024];
snprintf(cdrv, sizeof cdrv, "%s/ww", bin);
char wdrv[1024];
snprintf(wdrv, sizeof wdrv, "%s/ww_ww", bin);
struct { const char *name; const char *path; int gated_on_existence; }
drivers[] = {
{ "cstage", cdrv, 0 },
{ "wwstage", wdrv, 1 },
{ NULL, NULL, 0 },
};
int n = (int)(sizeof rows / sizeof rows[0]);
int total = 0, fail = 0;
/* Compile+run for each (driver, row). */
for (int d = 0; drivers[d].name; d++) {
if (drivers[d].gated_on_existence
&& access(drivers[d].path, X_OK) != 0) {
fprintf(stderr, "cgreturn_struct: skip %s (no %s)\n",
drivers[d].name, drivers[d].path);
continue;
}
for (int i = 0; i < n; i++) {
int got = run_driver(drivers[d].path, &rows[i], i);
total++;
if (got != rows[i].want) {
fprintf(stderr,
"cgreturn_struct[%s][%s]: exit=%d want=%d\n",
drivers[d].name, rows[i].label,
got, rows[i].want);
fail++;
}
}
}
/* Asm byte-identity diff, only when both stages exist. */
if (access(wdrv, X_OK) == 0) {
for (int i = 0; i < n; i++) {
total++;
if (asm_byte_identical(bin, &rows[i], i) != 0)
fail++;
}
}
if (fail) {
fprintf(stderr,
"cgreturn_struct: %d/%d fixtures failed\n", fail, total);
return 1;
}
printf("cgreturn_struct: %d/%d ok\n", total, total);
return 0;
}