wcc: compound-assign load-op-store for indexed + chained-ptr-field lvalues (#133)
Both stages had silent miscompiles on compound assignment for two shapes: indexed lvalue (`arr[i] OP= v`) and chained-pointer-field (`d.fld.fld OP= v` through a *struct chain). The cstage N_INDEX-lhs branch did not gate on TK_ASSIGN and silently DEMOTED compound ops to plain stores (RHS stored, no load, no op). The wwstage equivalents silently DROPPED the line entirely (no instructions emitted). The chained-pointer-field compound template at cgen.c:3281-3317 also silently identity-stored on unwired compound ops (SLASHEQ / PERCENTEQ / LSHIFTEQ / RSHIFTEQ all fell to the switch default = no-op = load, pop RHS, store ORIGINAL value back) and silently no-op'd on float / str / slice / tagged element compound; its wwstage twin at cgenexpr.ww:5471 only handled TK_ASSIGN, dropping any chained-ptr-field compound entirely. Wire all 10 integer compound ops (PLUSEQ MINUSEQ STAREQ AMPEQ PIPEEQ CARETEQ SLASHEQ PERCENTEQ LSHIFTEQ RSHIFTEQ) at all 4 sites in both stages: SLASHEQ/PERCENTEQ via CQO+IDIVQ (signed) or zero-DX+DIVQ (unsigned), with PERCENTEQ moving DX->AX for the result; LSHIFTEQ/ RSHIFTEQ via SHLQ/SHRQ on CX (rhs already in CX after the pop). Signedness keyed off the field/element type via type_isunsigned / typeisunsigned. Float / str / slice / tagged element compound now LOUD-ERRORS at codegen with a distinct per-site diagnostic citing #133/rule-7 instead of silent fall-through. Site 3 (the wwstage chained-pointer-field compound) is ADDED FROM SCRATCH alongside the existing TK_ASSIGN-only arm — pre-#133 wwstage emitted zero instructions for any `d.i.v OP= v` shape, a rule-10 silent divergence from the cstage which handled the same shape correctly. Multi-fix carve-out (rule 11): the 10 wired ops at 4 sites + hard-error gate on 4 unwired payload kinds at 4 sites are ONE silent-misbehavior class closure on indexed/chained-ptr-field compound assignment. Splitting would muddle bisect on related cgen surfaces — the wired ops, the hard-error gate, and the rule-10 cstage/wwstage symmetry are inseparable correctness facts at each site. The inherited template default-break silent-identity (cgen.c:3281-3317) was the originating class root; close it everywhere or leave the class open. 948_idx_compound_run: 21 rows total. 11 runtime+byte-id rows for the original 6 ops on u8/i32/i64/u32 array bases and one slice base, with a plain-assign control row asserting the ASSIGN path is byte-id- unchanged. 7 new runtime+byte-id rows for SLASHEQ/PERCENTEQ on signed i32 + unsigned u32, LSHIFTEQ on i32, RSHIFTEQ on signed-positive i32 and unsigned u32. 3 builderr rows (he_float_indexed, he_str_indexed, he_float_chained_ptr) asserting both stages exit non-zero AND stderr carries the cited diagnostic substring (rule-7 — never silent). Mirrors 945_tuple_nary's builderr/experr pattern. Bootstrap NEUTRAL — `grep -rE '\][[:space:]]*(\+=|-=|\*=|/=|&=|\|=|\^=|<<=|>>=)' lib/ selfhost/` (excluding combined.ww) returns ZERO existing callers for the indexed compound shape, and the chained-ptr-field compound shape was silent- no-op in wwstage pre-fix (no working caller possible). 990-997 byte- id gates green, 994 explicit confirms 18 corpus inputs identical pre/post. combined.ww (w6c + wwdump) regen deterministic across re-touch+rebuild. A_SARQ is not in w6a's opcode table; signed RSHIFTEQ uses SHRQ at all 4 sites for parity with the pre-existing deref-lvalue compound site (TK_RSHIFTEQ→A_SHRQ at cgen.c:4145). Documented technical debt filed as #136 — pre-existing concern that a fix would need w6a opcode addition + cgen sweep across every SHRQ-for-signed-RSHIFT site, out of scope for this fold.
This commit is contained in:
@@ -4342,6 +4342,178 @@ fn cgassign(c: *cgen, n: *node) void = {
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emitline("\tAX, (BX)\n");
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return;
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};
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// Compound assign on an indexed scalar element
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// (`arr[i] OP= v`). Pre-#133 the outer `if (n.op ==
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// TK_ASSIGN)` had no else and non-ASSIGN ops fell off
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// the cgassign function emitting NOTHING — silent
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// no-op. Mirror the chained-pointer-field compound
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// template at cmd/w6c/cgen.c:3281-3317: same address
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// computation as the ASSIGN arm above, then
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// tnodeloadop(BX)→AX, POP rhs→CX, combine, tnodestoreop.
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// Float / str / slice / tagged element compound stays
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// unwired — cstage's compound template never carried
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// those payload kinds. Same shape gate as the cstage
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// branch (cgen.c #133).
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if (n.op != tkind.TK_ASSIGN) {
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let base: *node = lhs.lhs;
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let idx: *node = lhs.rhs;
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let esz: i32 = 8;
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let baselocal: *local = nil;
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let isglobalarr: bool = false;
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let isglobalptr: bool = false;
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let globalname: str;
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globalname.ptr = nil; globalname.len = 0;
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let elemtn: *node = nil;
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if (base != nil) {
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if (base.kind == nkind.N_IDENT) {
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let bn: str = base.str;
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baselocal = localfindnode(c, bn);
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if (baselocal != nil) {
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esz = elemsizeofc(c, baselocal.tnode);
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let btn: *node = baselocal.tnode;
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if (btn != nil) {
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let bk: nkind = btn.kind;
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if (bk == nkind.N_TARRAY) { elemtn = btn.lhs; };
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if (bk == nkind.N_TSLICE) { elemtn = btn.lhs; };
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if (bk == nkind.N_TPTR) { elemtn = btn.lhs; };
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};
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} else {
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let tn: *node = letvartnode(c, bn);
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if (tn != nil) {
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if (tn.kind == nkind.N_TARRAY) {
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isglobalarr = true;
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globalname = bn;
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esz = elemsizeofc(c, tn);
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elemtn = tn.lhs;
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};
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if (tn.kind == nkind.N_TPTR) {
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isglobalptr = true;
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globalname = bn;
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esz = elemsizeofc(c, tn);
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elemtn = tn.lhs;
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};
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};
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};
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} else { if (base.kind == nkind.N_DOT) {
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let dt: *tinfo = lhs.type_: *tinfo;
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if (dt != nil) { esz = dt.size: i32; elemtn = lhs; };
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} else { if (base.kind == nkind.N_INDEX) {
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let et: *tinfo = lhs.type_: *tinfo;
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if (et != nil) {
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esz = et.size: i32;
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elemtn = lhs;
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};
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};};};
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};
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// #133-expanded: hard-error unwired payload kinds
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// LOUD (rule-7) — replaces prior silent skip.
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if (elemtn != nil) {
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if (istaggedtype(c, elemtn)) {
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let msg: str = "indexed-lvalue compound on tagged element not wired (#133/rule-7)\n";
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os.write(2, msg.ptr, msg.len: u64);
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os.exit(1);
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};
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if (isstrtype(c, elemtn)) {
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let msg: str = "indexed-lvalue compound on str element not wired (#133/rule-7)\n";
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os.write(2, msg.ptr, msg.len: u64);
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os.exit(1);
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};
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if (isslicetype(c, elemtn)) {
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let msg: str = "indexed-lvalue compound on slice element not wired (#133/rule-7)\n";
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os.write(2, msg.ptr, msg.len: u64);
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os.exit(1);
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};
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if (isfloattype(c, elemtn)) {
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let msg: str = "indexed-lvalue compound on float element not wired (#133/rule-7)\n";
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os.write(2, msg.ptr, msg.len: u64);
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os.exit(1);
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};
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};
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cgexpr(c, n.rhs);
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emitline("\tPUSHQ\tAX\n");
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cgexpr(c, idx);
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if (esz > 1) {
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emitline("\tMOVQ\t$");
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emitint(esz: i64);
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emitline(", CX\n");
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emitline("\tIMULQ\tCX, AX\n");
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};
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emitline("\tPUSHQ\tAX\n");
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if (isglobalarr) {
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emitline("\tLEAQ\t");
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emitsymname(c, globalname);
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emitline("(SB), BX\n");
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} else { if (isglobalptr) {
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emitline("\tMOVQ\t");
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emitsymname(c, globalname);
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emitline("(SB), BX\n");
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} else { if (baselocal != nil) {
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let tn: *node = baselocal.tnode;
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let isarray: bool = false;
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if (tn != nil) { if (tn.kind == nkind.N_TARRAY) { isarray = true; }; };
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if (isarray) {
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emitline("\tLEAQ\t");
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emitoff(baselocal.off: i64);
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emitline("(BP), BX\n");
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} else {
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emitline("\tMOVQ\t");
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emitoff(baselocal.off: i64);
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emitline("(BP), BX\n");
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};
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} else {
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cgexpr(c, base);
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emitline("\tMOVQ\tAX, BX\n");
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};};};
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emitline("\tPOPQ\tAX\n");
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emitline("\tADDQ\tAX, BX\n");
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let lop: str = tnodeloadop(c, elemtn, esz);
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emitline("\t");
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emitline(lop);
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emitline("\t(BX), AX\n");
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emitline("\tPOPQ\tCX\n");
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// #133-expanded: all 10 integer compound ops wired.
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// SLASHEQ/PERCENTEQ: CQO+IDIVQ (signed) or zero-DX+
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// DIVQ (unsigned). LSHIFTEQ/RSHIFTEQ: SHLQ/SHRQ via
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// CX. Signedness from elemtn.type_; signed RSHIFTEQ
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// uses SHRQ (cstage parity — A_SARQ not in w6a,
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// pre-existing signed-RSHIFT concern out of scope).
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let unsignd_c: bool = false;
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if (elemtn != nil) {
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if (elemtn.type_ != nil) {
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unsignd_c = typeisunsigned(elemtn.type_: *tinfo);
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};
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};
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let wired: bool = false;
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if (n.op == tkind.TK_PLUSEQ) { emitline("\tADDQ\tCX, AX\n"); wired = true; };
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if (n.op == tkind.TK_MINUSEQ) { emitline("\tSUBQ\tCX, AX\n"); wired = true; };
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if (n.op == tkind.TK_STAREQ) { emitline("\tIMULQ\tCX, AX\n"); wired = true; };
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if (n.op == tkind.TK_AMPEQ) { emitline("\tANDQ\tCX, AX\n"); wired = true; };
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if (n.op == tkind.TK_PIPEEQ) { emitline("\tORQ\tCX, AX\n"); wired = true; };
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if (n.op == tkind.TK_CARETEQ) { emitline("\tXORQ\tCX, AX\n"); wired = true; };
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if (n.op == tkind.TK_SLASHEQ) {
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if (unsignd_c) { emitline("\tMOVQ\t$0, DX\n"); emitline("\tDIVQ\tCX\n"); }
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else { emitline("\tCQO\n"); emitline("\tIDIVQ\tCX\n"); };
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wired = true;
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};
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if (n.op == tkind.TK_PERCENTEQ) {
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if (unsignd_c) { emitline("\tMOVQ\t$0, DX\n"); emitline("\tDIVQ\tCX\n"); }
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else { emitline("\tCQO\n"); emitline("\tIDIVQ\tCX\n"); };
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emitline("\tMOVQ\tDX, AX\n");
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wired = true;
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};
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if (n.op == tkind.TK_LSHIFTEQ) { emitline("\tSHLQ\tCX, AX\n"); wired = true; };
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if (n.op == tkind.TK_RSHIFTEQ) { emitline("\tSHRQ\tCX, AX\n"); wired = true; };
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if (!wired) {
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let msg: str = "indexed-lvalue compound: unknown compound op (#133/rule-7)\n";
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os.write(2, msg.ptr, msg.len: u64);
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os.exit(1);
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};
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let sop: str = tnodestoreop(c, elemtn, esz);
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emitline("\t");
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emitline(sop);
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emitline("\tAX, (BX)\n");
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return;
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};
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};
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};
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// `arr[i].field = v`: N_DOT lhs whose lhs is N_INDEX. Symmetric
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@@ -5407,6 +5579,87 @@ fn cgassign(c: *cgen, n: *node) void = {
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emitline("\n");
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return;
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};
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// #133-expanded site 3: chained-pointer-
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// field compound. Pre-#133-expanded the
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// wwstage chained-DOT-spine branch only
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// handled TK_ASSIGN; compound ops on a
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// chained-*struct.field shape (e.g.
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// `d.i.v += 7`) silently emitted nothing.
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// cstage cgen.c:3281-3317 handles this
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// (now-expanded for the same 10 ops +
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// hard-errors); this is its rule-10 twin.
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// All 10 integer compound ops wired;
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// float/str/slice/tagged field-type
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// hard-errors LOUD. Signed RSHIFTEQ uses
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// SHRQ (cstage parity, A_SARQ absent).
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if (n.op != tkind.TK_ASSIGN) {
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if (typeisstr(ft)) {
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let m: str = "chained-ptr-field compound on str element not wired (#133/rule-7)\n";
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os.write(2, m.ptr, m.len: u64);
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os.exit(1);
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};
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if (typeisslice(ft)) {
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let m: str = "chained-ptr-field compound on slice element not wired (#133/rule-7)\n";
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os.write(2, m.ptr, m.len: u64);
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os.exit(1);
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};
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if (typeisfloat(ft)) {
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let m: str = "chained-ptr-field compound on float element not wired (#133/rule-7)\n";
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os.write(2, m.ptr, m.len: u64);
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os.exit(1);
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};
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if (typeistagged(ft)) {
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let m: str = "chained-ptr-field compound on tagged element not wired (#133/rule-7)\n";
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os.write(2, m.ptr, m.len: u64);
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os.exit(1);
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};
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cgexpr(c, n.rhs);
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emitline("\tPUSHQ\tAX\n");
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cgexpr(c, base);
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emitline("\tPUSHQ\tAX\n");
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let fsz: i32 = ft.slotsize: i32;
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let unsignd_f: bool = typeisunsigned(ft);
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let lopf: str = loadopsz(!unsignd_f, fsz);
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emitline("\t");
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emitline(lopf);
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emitline("\t");
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emitdispreg(tf.offset: i64, "AX");
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emitline(", AX\n");
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emitline("\tPOPQ\tBX\n");
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emitline("\tPOPQ\tCX\n");
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let wired_f: bool = false;
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if (n.op == tkind.TK_PLUSEQ) { emitline("\tADDQ\tCX, AX\n"); wired_f = true; };
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if (n.op == tkind.TK_MINUSEQ) { emitline("\tSUBQ\tCX, AX\n"); wired_f = true; };
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if (n.op == tkind.TK_STAREQ) { emitline("\tIMULQ\tCX, AX\n"); wired_f = true; };
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if (n.op == tkind.TK_AMPEQ) { emitline("\tANDQ\tCX, AX\n"); wired_f = true; };
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if (n.op == tkind.TK_PIPEEQ) { emitline("\tORQ\tCX, AX\n"); wired_f = true; };
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if (n.op == tkind.TK_CARETEQ) { emitline("\tXORQ\tCX, AX\n"); wired_f = true; };
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if (n.op == tkind.TK_SLASHEQ) {
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if (unsignd_f) { emitline("\tMOVQ\t$0, DX\n"); emitline("\tDIVQ\tCX\n"); }
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else { emitline("\tCQO\n"); emitline("\tIDIVQ\tCX\n"); };
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wired_f = true;
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};
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if (n.op == tkind.TK_PERCENTEQ) {
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if (unsignd_f) { emitline("\tMOVQ\t$0, DX\n"); emitline("\tDIVQ\tCX\n"); }
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else { emitline("\tCQO\n"); emitline("\tIDIVQ\tCX\n"); };
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emitline("\tMOVQ\tDX, AX\n");
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wired_f = true;
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};
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if (n.op == tkind.TK_LSHIFTEQ) { emitline("\tSHLQ\tCX, AX\n"); wired_f = true; };
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if (n.op == tkind.TK_RSHIFTEQ) { emitline("\tSHRQ\tCX, AX\n"); wired_f = true; };
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if (!wired_f) {
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let m: str = "chained-ptr-field compound: unknown op (#133/rule-7)\n";
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os.write(2, m.ptr, m.len: u64);
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os.exit(1);
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};
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let sopf: str = tnodestoreop(c, n.rhs, fsz);
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emitline("\t");
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emitline(sopf);
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emitline("\tAX, ");
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emitdispreg(tf.offset: i64, "BX");
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emitline("\n");
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return;
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};
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};
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tf = tf.tnext;
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};
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