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refactor a20.c

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Hojun-Cho 2024-12-05 18:00:09 +09:00
parent 06c375cac5
commit 7acbe88026
1 changed files with 19 additions and 23 deletions
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42
boot/a20.c
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@ -1,35 +1,31 @@
#include <u.h> #include <u.h>
#include "fn.h" #include "fn.h"
#define I8042_DPORT 0x60
#define I8042_SPORT 0x64
#define I8042_CPORT 0x64
#define I8042_IN_FULL 0x02
#define I8042_DATA_FULL 0x01
#define I8042_OUT 0xd1
#define I8042_A20_UP 0xdf // 0xD0 | a20 | clock | buffer full IRQ1
// https://wiki.osdev.org/%228042%22_PS/2_Controller#Initialising_the_PS/2_Controller
void void
a20up(void) a20up(void)
{ {
struct{ while(inb(I8042_SPORT) & I8042_IN_FULL)
int dport, sport, cport;
u8 a20;
u8 dib, ib, wout;
} i8042 = {
.dport = 0x60, // data port
.sport = 0x64, // status register port
.cport = 0x64, // command register port
.a20 = 0xdf, // enable a20 line value
.dib = 0x01, // kbd data in buffer
.ib = 0x02, // kbd input buffer
.wout = 0xd1, // write output port value
};
while(inb(i8042.sport) & i8042.ib)
; ;
while(inb(i8042.sport) & i8042.dib) while(inb(I8042_SPORT) & I8042_DATA_FULL)
inb(i8042.dport); inb(I8042_DPORT);
outb(i8042.cport, i8042.wout); outb(I8042_CPORT, I8042_OUT);
while(inb(i8042.sport) & i8042.ib) // wait until input buffer is empty
while(inb(I8042_SPORT) & I8042_IN_FULL)
; ;
outb(i8042.dport, i8042.a20); outb(I8042_DPORT, I8042_A20_UP);
while(inb(i8042.sport) & i8042.ib) while(inb(I8042_SPORT) & I8042_IN_FULL)
; ;
while(inb(i8042.sport) & i8042.dib) while(inb(I8042_SPORT) & I8042_DATA_FULL)
inb(i8042.dport); inb(I8042_DPORT);
} }