The wwstage tagged widen's struct-payload classify was name-keyed:
rhsstructpayload's N_IDENT arm did a bare structlookup on the local's
declared TNAME, so an alias name (ali->base) missed the registered
structinfo and the value fell past the struct arm to the SCALAR widen
arm — word0-only box payload, words 1+ zero-filled. At normal decl
order this was BOTH-WRONG-IDENTICAL with cstage pre-F1 (byte-id YES,
gate-blind; F0 m5b_match1 exit 2/2). Choke-point fix: route the arm
through structlookupchain (the name-domain twin of cstage's
su = type_chase_named, c138605) and return the REGISTERED struct
name so every consumer's re-lookup hits. All three consumers
graduate through the one funnel (proof-grep: rhsstructpayload is the
only struct-payload classifier): cgwidentaggedstorebp's struct arm
(let/assign/match), pushargsrev's widen route (the call-arg twin),
and cgreturn's needswiden (cgenstmt.ww:1022). The variant TAG still
keys on the un-chased stamped type — the member's nominal identity
is the alias (cg_tag_for_variant precedent).
Rider, same store family: cgwidentaggedstorebp now chases the source
classify ONCE at entry (post cast peels, where src is final) —
`su = tichase(src.type_)` replaces the five per-arm chases
(nested-arm su / memread su37 / >32B+cast-guard sf37 / tuple-guard
stu72 / tuple-arm stu, all reading the same src.type_), mirroring
cstage cg_widen_tagged_store's su position. dt entry loop + the
remaining in-function plain chases (castu/ceti/fti/fvt) collapse to
tichase — mechanical, excluded from c1 only because the function was
c2 scope wholesale.
Runtime graduation (banked rows .ai/impl62r_layer2_rows.md):
m5b_match1 (L2-1 norm) + m5_match (L2-2 fwd) cs0/ww2 -> 0/0 byte-id;
L2-4 3-word (last payload word) 0/0; push-twin arg row 0/0; control
m5b_match0 holds 0/0 (ken confirms at verdict). test 944: the four
K_RUN_CS rows flip to K_RUN (both drivers + byte-id), 129/129.
SURFACED, FILED NOT FIXED (task #89): the RETURN-position leg
(`return x` of an alias struct into a (void|ali) fn return) was
both-wrong-identical (cs1/ww1 byte-id) and is now transiently
cs1/ww0 byte-id NO — ww is the runtime-correct side; cstage
cgreturn's own route into the widen misses the alias (F1 c138605
covered store+push only). F1-precedent transient divergence, noted
per the L2 rows file's acceptance clause.
Selfhost byte-id: new w6c_ww on the c1-HEAD five main.combined.ww —
byte-identical to the c1 build's output (the fix is asm-neutral on
the corpus); cs==ww on the regenerated five. make test-unit green
(288). Closes task #62's ww half — fix-landed-pending-gate (#71
precedent). combined.ww regens ride along.
Hojun-Cho
f7fd3e4850