Hojun-Cho
057e805cf0
949_dotfield_compound + 949_idxfield_compound are one bug class (#133-lineage compound-assign load-op-store on field lvalues; #34/#33, #263 carve-out) sharing the combine + hard-error path, so the two C carriers fuse into one commit: 26 value rows -> test/lang @test row-tables (primitive-only asserts), 8 reject rows -> runww //ww:error dual-stage carriers. byteid floor 50->52.
117 lines
3.3 KiB
Plaintext
117 lines
3.3 KiB
Plaintext
// idxfield_compound_test — indexed-element field compound-assign (#33, #263
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// both stages), migrated from test/wcc/949_idxfield_compound_run.c. A compound
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// assign on an indexed-element FIELD lvalue (`arr[i].field OP= v`) must do a
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// real LOAD-OP-STORE for ALL ten integer ops, not silently no-op the four the
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// arm never wired (SLASHEQ/PERCENTEQ/LSHIFTEQ/RSHIFTEQ loaded the old value
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// into AX, fired no combine, and stored AX back — a silent no-op in BOTH
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// stages, gate-blind/byte-identical). Every row init-poisons xs[0].f with a
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// value != the expected result, runs the op, reads the field back, and asserts
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// a sibling slot (xs[0].g or xs[1].f) is UNTOUCHED to catch an over-wide /
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// wrong-offset store. PRIMITIVE-only asserts (no fmt/strconv) so a co-
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// miscompile in the assert path cannot mask the bug. The matrix covers
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// + * / % << >> across i32/i64/u32 fields and a via-ptr element ([N]*S); the
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// plain-assign control pins the ASSIGN path the fix must leave unchanged. T2
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// keeps cs==ww.
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package idxfield_compound_test;
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type S32 = struct { f: i32, g: i32 };
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type S64 = struct { f: i64, g: i64 };
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type Su32 = struct { f: u32, g: u32 };
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@test fn fld_i32_pluseq() void = {
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let xs: [2]S32 = [S32{f=100, g=0}, S32{f=0, g=0}];
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xs[0].f += 50;
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assert(xs[0].f == 150);
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assert(xs[0].g == 0);
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assert(xs[1].f == 0);
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};
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@test fn fld_i64_stareq() void = {
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let xs: [2]S64 = [S64{f=6i64, g=0i64}, S64{f=0i64, g=0i64}];
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xs[0].f *= 7i64;
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assert(xs[0].f == 42i64);
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assert(xs[0].g == 0i64);
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assert(xs[1].f == 0i64);
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};
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@test fn fld_i32_slasheq() void = {
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let xs: [2]S32 = [S32{f=100, g=0}, S32{f=0, g=0}];
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xs[0].f /= 4;
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assert(xs[0].f == 25);
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assert(xs[0].g == 0);
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assert(xs[1].f == 0);
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};
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@test fn fld_i32_slasheq_neg() void = {
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let xs: [2]S32 = [S32{f=-17, g=0}, S32{f=0, g=0}];
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xs[0].f /= 4;
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assert(xs[0].f == -4);
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assert(xs[0].g == 0);
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assert(xs[1].f == 0);
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};
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@test fn fld_u32_slasheq() void = {
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let xs: [2]Su32 = [Su32{f=100u32, g=0u32}, Su32{f=0u32, g=0u32}];
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xs[0].f /= 4u32;
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assert(xs[0].f == 25u32);
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assert(xs[0].g == 0u32);
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assert(xs[1].f == 0u32);
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};
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@test fn fld_i32_percenteq() void = {
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let xs: [2]S32 = [S32{f=17, g=0}, S32{f=0, g=0}];
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xs[0].f %= 5;
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assert(xs[0].f == 2);
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assert(xs[0].g == 0);
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assert(xs[1].f == 0);
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};
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@test fn fld_u32_percenteq() void = {
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let xs: [2]Su32 = [Su32{f=100u32, g=0u32}, Su32{f=0u32, g=0u32}];
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xs[0].f %= 7u32;
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assert(xs[0].f == 2u32);
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assert(xs[0].g == 0u32);
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assert(xs[1].f == 0u32);
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};
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@test fn fld_i32_lshifteq() void = {
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let xs: [2]S32 = [S32{f=3, g=0}, S32{f=0, g=0}];
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xs[0].f <<= 4;
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assert(xs[0].f == 48);
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assert(xs[0].g == 0);
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assert(xs[1].f == 0);
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};
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@test fn fld_u32_rshifteq() void = {
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let xs: [2]Su32 = [Su32{f=200u32, g=0u32}, Su32{f=0u32, g=0u32}];
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xs[0].f >>= 2u32;
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assert(xs[0].f == 50u32);
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assert(xs[0].g == 0u32);
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assert(xs[1].f == 0u32);
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};
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@test fn fld_i32_rshifteq_neg() void = {
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let xs: [2]S32 = [S32{f=-16, g=0}, S32{f=0, g=0}];
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xs[0].f >>= 2;
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assert(xs[0].f == -4);
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assert(xs[0].g == 0);
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assert(xs[1].f == 0);
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};
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@test fn fld_viaptr_pluseq() void = {
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let a: S32 = S32{f=10, g=0};
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let xs: [2]*S32 = [&a, &a];
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xs[0].f += 5;
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assert(a.f == 15);
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assert(a.g == 0);
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};
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@test fn fld_plain_assign_ctrl() void = {
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let xs: [2]S32 = [S32{f=1, g=0}, S32{f=0, g=0}];
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xs[0].f = 99;
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assert(xs[0].f == 99);
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assert(xs[0].g == 0);
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assert(xs[1].f == 0);
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};
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