Hojun-Cho
ce3a25a0b4
The wcc test drivers ran `ww build <bare-/tmp src>` with no -o, so the compiler's <stem>.sepwork scratch landed beside the source and was never cleaned: unbounded /tmp growth (2195 stale dirs observed) that fills tmpfs and fabricates phantom test failures + silent harness aborts, and for in-repo fixture builds leaked .sepwork into the tracked tree. Each leaking build now writes its source + output inside a per-invocation tmpdir, passes -o <tmpdir>/<stem> so the .sepwork lands inside it, and rm -rf's the tmpdir on every exit path -- including fopen-fail and the expected-fail reject builds (scratch is mkdir'd before the build can fail). `ww run` and explicit-`-o`/byte-id helpers are left as-is; the 990/993 byte-id comparison logic is byte-for-byte unchanged. Two items filed separately (this commit holds the no-Makefile / no-main.c rail): - #13: a stale <src>.s byte-id readback (749) silently no-ops since separate-compile emits .s to <ostem>.sepwork/__root.s; documented inline. - #14: build-system Makefile recipes build selfhost/cmd/*/main.ww with no -o and leak main.sepwork in-tree (bounded, gitignored; own commit). One concern -- sepwork leak hygiene -- across 228 drivers; uniform transform applied per-file and two-round reviewed. make test: all 402 passed, zero net-new /tmp scratch, zero test-driven in-repo .sepwork.
399 lines
13 KiB
C
399 lines
13 KiB
C
/*
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* 683_arr_strslice_elem — cstage and wwstage agree, byte-for-byte and
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* at runtime, that an `[N][]u8` / `[N]str` array-LITERAL init copies the
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* FULL 24B {ptr,len,cap} header of every element (task #20, the #270
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* aggregate-element-store family's str/slice arm).
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*
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* The bug: cgen's N_LET / N_ARRLIT per-element store lowered each str/
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* slice element's header into AX=ptr/BX=len/CX=cap (cgexpr) but stored
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* only some words — a slice element fell through to the scalar 1-word
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* MOVQ (dropping .len AND .cap), and a str element stored 2 words
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* (dropping .cap, latent). Each element is 24B and must be copied
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* whole. wwstage was worse: a slice element matched no esz branch, so
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* esz stayed the 8 sentinel — the per-element stride collapsed (element
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* i+1 overwrote element i's tail), the -96-vs-80 cs!=ww frame
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* divergence. struct/array/tuple elements already copied correctly via
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* the #270-1c is_agg multi-word path; str/slice were the documented
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* follow-up (cgen.c:9037-9042, cgenstmt.ww deferral comment).
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*
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* The fix (BOTH stages, converged byte-identical): cstage adds
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* is_slice_el = type_isslice(esub) and stores 3 words (incl CX->base+16)
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* for `is_str_el || is_slice_el`; wwstage adds isslicel (TY_SLICE ->
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* esz = esubti.size, fixing the stride) and the matching 3-word store.
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*
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* Cap is validated BOTH ways: a WHOLE-ELEMENT COPY (`let q = t[i]; q.cap`)
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* AND a DIRECT `t[i].cap` read. The direct read was a SEPARATE bug (task
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* #13, the #20 store's read-sibling): the `.cap` field-extract on an
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* INDEXED slice/str element returned .ptr on cstage (it shuffled only
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* .len BX→AX, leaving AX=.ptr for cap) and emitted NO read on wwstage
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* (the cgdot non-ident catch-all handled only .ptr/.len) — divergent.
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* Fix (BOTH stages, byte-id): cgexpr leaves the full {ptr,len,cap} header
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* via cgslicehdr for an indexed element, so .cap shuffles CX→AX, the twin
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* of the .len BX→AX shuffle. The direct-cap rows must equal the
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* whole-element-copy oracle (which #20 made correct).
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*
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* Mutation-sanity (the per-word coverage): the .len rows fail if the
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* store drops the .len word (the pre-fix slice 1-word store), and the
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* cap-via-copy rows fail if it drops the .cap word (the pre-fix str
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* 2-word store) — so a regression to a 1-word or 2-word store is caught.
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*
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* row | shape | want
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* -----------------+------------------------------------+--------------
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* slice_len1 | [2][]u8, return t[1].len. Pre-fix | 2 + byte-id
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* | slice 1-word store dropped .len. |
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* slice_len0 | [2][]u8, return t[0].len. | 3 + byte-id
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* slice_stride3 | [3][]u8, return t[2].len. Exercises| 7 + byte-id
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* | the 24B per-element stride (the |
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* | wwstage 8-sentinel frame-offset |
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* | bug overran into the wrong slot). |
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* slice_cap_copy | [2][]u8 w/ caps 7,6; let q=t[0]; | 7 + byte-id
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* | return q.cap. Validates the stored |
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* | .cap word (pre-fix dropped). |
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* slice_ptr | [2][]u8 over a backing array; let | 4 + byte-id
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* | q=t[1]; return q[0]. Pins .ptr |
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* | stored correctly (deref the elem). |
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* str_len1 | [2]str=[a,b], return t[1].len. | 2 + byte-id
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* str_cap_copy | [2]str=["abcde","xy"]; let q=t[0]; | 5 + byte-id
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* | return q.cap. The latent str cap- |
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* | drop (pre-fix garbage); cap=len=5 |
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* | for a static literal. |
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* struct_elem | [2]Pt struct literal, return | 4 + byte-id
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* | t[1].y. Regression pin: the is_agg |
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* | multi-word path is untouched by |
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* | the str/slice branch. |
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*
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* Exit-code rows confirm both stages run correctly. The asm-byte-id rows
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* pin the symmetric 3-word store (cstage == wwstage); pre-fix wwstage
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* mis-strided (slice esz=8) and under-copied, so the diff was non-empty.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <sys/stat.h>
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#include <sys/wait.h>
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static int
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runwait(const char *cmd)
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{
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int rc = system(cmd);
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if (rc == -1) return -1;
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if (WIFEXITED(rc)) return WEXITSTATUS(rc);
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return -1;
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}
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/* want == BYTEID_ONLY: the row's runtime value is non-deterministic (a
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* link-time address), so only the cstage/wwstage asm-byte-id is asserted;
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* the build must still succeed on both stages. Used for the `"abc".cap`
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* symmetry edge (a string-literal .cap is meaningless garbage on both
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* stages, but rule 10 still requires byte-identical asm). */
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#define BYTEID_ONLY (-2147483647 - 1)
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struct row { const char *label; const char *src; int want; };
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static const struct row rows[] = {
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{ "slice_len1",
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"package main;\n"
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"export fn main() i32 = {\n"
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"\tlet hb: [8]u8;\n"
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"\tlet a: []u8; a.ptr = &hb[0]; a.len = 3; a.cap = 8;\n"
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"\tlet b: []u8; b.ptr = &hb[0]; b.len = 2; b.cap = 8;\n"
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"\tlet t: [2][]u8 = [a, b];\n"
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"\treturn t[1].len: i32;\n"
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"};\n",
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2 },
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{ "slice_len0",
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"package main;\n"
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"export fn main() i32 = {\n"
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"\tlet hb: [8]u8;\n"
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"\tlet a: []u8; a.ptr = &hb[0]; a.len = 3; a.cap = 8;\n"
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"\tlet b: []u8; b.ptr = &hb[0]; b.len = 2; b.cap = 8;\n"
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"\tlet t: [2][]u8 = [a, b];\n"
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"\treturn t[0].len: i32;\n"
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"};\n",
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3 },
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{ "slice_stride3",
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"package main;\n"
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"export fn main() i32 = {\n"
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"\tlet hb: [8]u8;\n"
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"\tlet a: []u8; a.ptr = &hb[0]; a.len = 3; a.cap = 8;\n"
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"\tlet b: []u8; b.ptr = &hb[0]; b.len = 5; b.cap = 8;\n"
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"\tlet c: []u8; c.ptr = &hb[0]; c.len = 7; c.cap = 8;\n"
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"\tlet t: [3][]u8 = [a, b, c];\n"
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"\treturn t[2].len: i32;\n"
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"};\n",
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7 },
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{ "slice_cap_copy",
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"package main;\n"
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"export fn main() i32 = {\n"
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"\tlet hb: [8]u8;\n"
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"\tlet a: []u8; a.ptr = &hb[0]; a.len = 3; a.cap = 7;\n"
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"\tlet b: []u8; b.ptr = &hb[0]; b.len = 2; b.cap = 6;\n"
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"\tlet t: [2][]u8 = [a, b];\n"
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"\tlet q: []u8 = t[0];\n"
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"\treturn q.cap: i32;\n"
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"};\n",
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7 },
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/* #13 direct-read rows: `t[i].cap` straight (no copy via a let).
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* Must equal the slice_cap_copy / str_cap_copy oracle. Pre-fix:
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* cstage returned .ptr (a heap/stack address, != 7/6), wwstage
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* emitted no read (stale AX) — and the two diverged. */
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{ "slice_cap_direct0",
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"package main;\n"
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"export fn main() i32 = {\n"
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"\tlet hb: [8]u8;\n"
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"\tlet a: []u8; a.ptr = &hb[0]; a.len = 3; a.cap = 7;\n"
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"\tlet b: []u8; b.ptr = &hb[0]; b.len = 2; b.cap = 6;\n"
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"\tlet t: [2][]u8 = [a, b];\n"
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"\treturn t[0].cap: i32;\n"
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"};\n",
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7 },
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{ "slice_cap_direct1",
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"package main;\n"
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"export fn main() i32 = {\n"
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"\tlet hb: [8]u8;\n"
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"\tlet a: []u8; a.ptr = &hb[0]; a.len = 3; a.cap = 7;\n"
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"\tlet b: []u8; b.ptr = &hb[0]; b.len = 2; b.cap = 6;\n"
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"\tlet t: [2][]u8 = [a, b];\n"
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"\treturn t[1].cap: i32;\n"
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"};\n",
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6 },
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{ "str_cap_direct0",
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"package main;\n"
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"export fn main() i32 = {\n"
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"\tlet a: str = \"abcde\";\n"
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"\tlet b: str = \"xy\";\n"
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"\tlet t: [2]str = [a, b];\n"
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"\treturn t[0].cap: i32;\n"
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"};\n",
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5 },
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{ "str_cap_direct1",
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"package main;\n"
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"export fn main() i32 = {\n"
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"\tlet a: str = \"abcde\";\n"
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"\tlet b: str = \"xy\";\n"
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"\tlet t: [2]str = [a, b];\n"
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"\treturn t[1].cap: i32;\n"
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"};\n",
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2 },
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/* #13 symmetry edge: `.cap` of a BARE string literal. The wwstage
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* checker types N_STRLIT as `str` (cstage types it untyped_str), so
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* the .cap kind-gate would wrongly shuffle CX→AX on wwstage only —
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* but a literal's cgexpr never loads a CX cap, and cstage never
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* shuffles it, so both must return AX (ptr) unshuffled. Byte-id only:
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* the value is a link-time address (non-deterministic). Pre-fix this
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* row's asm DIFFERED (wwstage had the stray MOVQ CX, AX). */
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{ "str_lit_cap_symmetry",
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"package main;\n"
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"export fn main() i32 = {\n"
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"\treturn \"abc\".cap: i32;\n"
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"};\n",
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BYTEID_ONLY },
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{ "slice_ptr",
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"package main;\n"
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"export fn main() i32 = {\n"
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"\tlet hb: [8]u8; hb[0] = 9u8; hb[1] = 4u8;\n"
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"\tlet a: []u8; a.ptr = &hb[0]; a.len = 3; a.cap = 8;\n"
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"\tlet b: []u8; b.ptr = &hb[1]; b.len = 2; b.cap = 8;\n"
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"\tlet t: [2][]u8 = [a, b];\n"
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"\tlet q: []u8 = t[1];\n"
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"\treturn q[0]: i32;\n"
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"};\n",
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4 },
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{ "str_len1",
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"package main;\n"
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"export fn main() i32 = {\n"
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"\tlet a: str = \"abc\";\n"
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"\tlet b: str = \"de\";\n"
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"\tlet t: [2]str = [a, b];\n"
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"\treturn t[1].len: i32;\n"
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"};\n",
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2 },
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{ "str_cap_copy",
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"package main;\n"
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"export fn main() i32 = {\n"
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"\tlet a: str = \"abcde\";\n"
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"\tlet b: str = \"xy\";\n"
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"\tlet t: [2]str = [a, b];\n"
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"\tlet q: str = t[0];\n"
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"\treturn q.cap: i32;\n"
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"};\n",
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5 },
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/* Regression pin: a [N]struct element copies multi-word via the
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* pre-existing #270-1c is_agg path, NOT the new str/slice 3-word
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* header branch. Proves the str/slice esz/store change leaves the
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* is_agg element path untouched (byte-id holds for it too). */
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{ "struct_elem",
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"package main;\n"
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"type Pt = struct { x: i32, y: i32 };\n"
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"export fn main() i32 = {\n"
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"\tlet t: [2]Pt = [Pt { x = 1, y = 2 }, Pt { x = 3, y = 4 }];\n"
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"\treturn t[1].y: i32;\n"
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"};\n",
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4 },
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};
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static int
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run_driver(const char *driver, const struct row *r, int i)
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{
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char tmpdir[64], src[128], outbin[128], rmcmd[160], cmd[1024];
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snprintf(tmpdir, sizeof tmpdir, "/tmp/asse_%d_d_%d", getpid(), i);
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mkdir(tmpdir, 0755);
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snprintf(src, sizeof src, "%s/asse_%d_%d.ww", tmpdir, getpid(), i);
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snprintf(outbin, sizeof outbin, "%s/asse_%d_%d", tmpdir, getpid(), i);
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snprintf(rmcmd, sizeof rmcmd, "rm -rf %s", tmpdir);
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FILE *f = fopen(src, "wb");
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if (!f) { runwait(rmcmd); return -1; }
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fputs(r->src, f);
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fclose(f);
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snprintf(cmd, sizeof cmd, "%s build -o %s %s 2>/dev/null",
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driver, outbin, src);
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if (runwait(cmd) != 0) {
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fprintf(stderr, "row[%s]: build via %s failed\n",
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r->label, driver);
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runwait(rmcmd);
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return -1;
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}
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int got = runwait(outbin);
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runwait(rmcmd);
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return got;
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}
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/* asm_byte_identical — generate .s via cstage's w6c and wwstage's
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* w6c_ww and diff. The regression-pinning row for #20: pre-fix wwstage
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* mis-strided the slice element (esz=8) and under-copied, so the diff
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* was non-empty; the converged 3-word store makes them identical. */
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static int
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asm_byte_identical(const char *bin, const struct row *r, int i)
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{
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char src[64], cs[64], ws[64], cmd[1024];
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snprintf(src, sizeof src, "/tmp/asse_asm_%d_%d.ww", getpid(), i);
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snprintf(cs, sizeof cs, "/tmp/asse_asm_%d_%d_c.s", getpid(), i);
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snprintf(ws, sizeof ws, "/tmp/asse_asm_%d_%d_w.s", getpid(), i);
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FILE *f = fopen(src, "wb");
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if (!f) return -1;
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fputs(r->src, f);
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fclose(f);
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snprintf(cmd, sizeof cmd, "%s/w6c -o %s %s 2>/dev/null", bin, cs, src);
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if (runwait(cmd) != 0) {
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fprintf(stderr, "row[%s]: w6c errored\n", r->label);
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unlink(src);
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return -1;
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}
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snprintf(cmd, sizeof cmd, "%s/w6c_ww -o %s %s 2>/dev/null",
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bin, ws, src);
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if (runwait(cmd) != 0) {
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fprintf(stderr, "row[%s]: w6c_ww errored\n", r->label);
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unlink(src); unlink(cs);
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return -1;
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}
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FILE *fc = fopen(cs, "rb");
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FILE *fw = fopen(ws, "rb");
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int rc = 0;
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if (!fc || !fw) {
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rc = -1;
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} else {
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for (;;) {
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int a = fgetc(fc);
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int b = fgetc(fw);
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if (a != b) { rc = -1; break; }
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if (a == EOF) break;
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}
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}
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if (fc) fclose(fc);
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if (fw) fclose(fw);
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if (rc != 0)
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fprintf(stderr, "row[%s]: cstage vs wwstage asm differs\n",
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r->label);
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unlink(src); unlink(cs); unlink(ws);
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return rc;
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}
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int
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main(void)
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{
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const char *bin = getenv("BIN");
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if (!bin) bin = "out/bin";
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char absbin[1024];
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if (bin[0] != '/') {
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char cwd[1024];
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if (getcwd(cwd, sizeof cwd) == NULL) return 1;
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snprintf(absbin, sizeof absbin, "%s/%s", cwd, bin);
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bin = absbin;
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}
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char cdrv[1024];
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snprintf(cdrv, sizeof cdrv, "%s/ww", bin);
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char wdrv[1024];
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snprintf(wdrv, sizeof wdrv, "%s/ww_ww", bin);
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struct { const char *name; const char *path; int gated_on_existence; }
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drivers[] = {
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{ "cstage", cdrv, 0 },
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{ "wwstage", wdrv, 1 },
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{ NULL, NULL, 0 },
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};
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int n = (int)(sizeof rows / sizeof rows[0]);
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int total = 0, fail = 0;
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for (int d = 0; drivers[d].name; d++) {
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if (drivers[d].gated_on_existence
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&& access(drivers[d].path, X_OK) != 0) {
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fprintf(stderr, "arr_strslice_elem: skip %s (no %s)\n",
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drivers[d].name, drivers[d].path);
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continue;
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}
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for (int i = 0; i < n; i++) {
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int got = run_driver(drivers[d].path, &rows[i], i);
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total++;
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/* BYTEID_ONLY rows assert asm byte-id below; here only
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* the build must succeed (run_driver returns -1 on a
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* build/run failure). The exit value is ignored. */
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int bad = rows[i].want == BYTEID_ONLY
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? (got == -1) : (got != rows[i].want);
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if (bad) {
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fprintf(stderr,
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"arr_strslice_elem[%s][%s]: exit=%d want=%d\n",
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drivers[d].name, rows[i].label,
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got, rows[i].want);
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fail++;
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}
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}
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}
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if (access(wdrv, X_OK) == 0) {
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for (int i = 0; i < n; i++) {
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total++;
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if (asm_byte_identical(bin, &rows[i], i) != 0)
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fail++;
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}
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}
|
|
|
|
if (fail) {
|
|
fprintf(stderr,
|
|
"arr_strslice_elem: %d/%d fixtures failed\n", fail, total);
|
|
return 1;
|
|
}
|
|
printf("arr_strslice_elem: %d/%d ok\n", total, total);
|
|
return 0;
|
|
}
|