Hojun-Cho
dc33af6217
The #173 remap loop in cgtryprop gated on the tparam's explicit `!` flag only; a LEGACY union (no marks anywhere) classifies error variants POSITIONALLY (index 0 is success, cstage cg_variant_is_error cgen.c:905) — so wwstage emitted no remap and propagated the callee's raw tag into a differently-ordered caller union, a silent wrong arm (cstage exit 7, wwstage 9 on the banked r700 row). Add the variantiserror twin and gate the loop on it; refresh the drifted cstage cite. Graduates the held e2e row into the corpus (pin 1727/1156/3454) and adds legacy-mode rows to test/lang/tryprop_tag_remap_test.ww: reversed order both directions, slot-0 remap, str payload integrity, a two-hop chain whose pre-fix runtime pass was double-miss tag cancellation (the lang byteid leg pins the emitted remap blocks), and a same-order zero-emission control.
22 lines
503 B
Plaintext
22 lines
503 B
Plaintext
//ww:run-exit 7
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// Migrated from 700_e2e row 69.
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package main;
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fn inner(n: i32) (i32 | str | bool) = {
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if (n == 0) { return "z"; };
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if (n < 0) { return false; };
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return n;
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};
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fn outer(n: i32) (i64 | bool | str) = {
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let v: i32 = inner(n)?;
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return v: i64 + 1000;
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};
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fn main() i32 = {
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let r: (i64 | bool | str) = outer(-1);
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match (r) {
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case let n: i64 => return n: i32;
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case let b: bool => { if (!b) { return 7; }; return 8; };
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case let s: str => return 9;
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};
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return 0;
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};
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