Wwstage cgassign's N_INDEX-lhs base-inspection (cgenexpr.ww) only
computed esz/elemtn when base.kind == N_IDENT or N_DOT. For a
chained `names[i][k] = v` (names: **u8) the outer N_INDEX has
base.kind == N_INDEX; esz fell through to the default 8 so the
outer store emitted `MOVQ AX, (BX)` into a 1-byte u8 slot (8 bytes
written — adjacent memory corrupted) plus a stray
`MOVQ $8, CX; IMULQ CX, AX` scaling on the outer index that cstage
doesn't emit. Wrong-width-store: the byte slot was written as 8
bytes and the outer offset multiplied by sizeof *u8 instead of
sizeof u8.
Cstage walks `n->lhs->type` directly via the typed AST at the
N_ASSIGN N_INDEX-lhs branch (cmd/w6c/cgen.c eff->sub->size = 1).
Wwstage now mirrors via indexvaluetnode (already graduated for
cgindex in #24, commit aa8ca47) — the cgassign N_INDEX-lhs branch
gains the parallel base-N_INDEX arm: call indexvaluetnode, then
elemsizeofc for esz and one-layer-strip for elemtn (so the tagged-
element gate keys honestly on the element type, matching the
N_IDENT branch's pattern).
Class A wwstage cgen UNDER. Sister latent of #24's surfaced read-
path bug; filed during the #24 graduation with selfhost + lib grep
empty for chained-write. No in-tree consumer surfaced this before
the fix, so test 740_chained_write is the sole exerciser — pins
cstage-byte-identical asm for **u8 (MOVB store, 1 inner-stride-8
IMULQ pair, no outer scale) + **i32 (MOVL store, inner $8 + outer
$4 IMULQ pairs). Anti-check on the u8 row guards against the pre-
fix stray `MOVQ AX, (BX)` regression.
Sister latents filed (no in-tree consumer):
cgassign N_DOT-base elemtn drop (sister of cgindex N_DOT-base
in #24 review): tagged-element store via obj.arr[i] over a
struct-field array falls through to scalar store.
114/114 ok. ww2 == ww3 == ww4 byte-id.
287 lines
8.6 KiB
C
287 lines
8.6 KiB
C
/*
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* 740_chained_write — sentinel for #27. Pins wwstage's cgassign to
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* compute the element size of the outer N_INDEX in `arr[i][k] = v`
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* from the value-type of the inner N_INDEX, instead of defaulting
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* to 8. Sister of 739_chained_index (#24, read path); same dispatch
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* gap on the write side.
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*
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* Pre-fix wwstage cgassign (selfhost/cmd/wcc/cgenexpr.ww) only
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* walked `base.kind == N_IDENT` and `base.kind == N_DOT` for the
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* esz/elemtn dispatch on the N_INDEX-lhs branch. When base was the
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* inner N_INDEX of a chained `names[i][k]` shape (names: **u8), esz
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* stayed at the default 8 and the store fell through to MOVQ — an
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* 8-byte write over a 1-byte u8 slot (corrupting adjacent memory),
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* plus a stray `MOVQ $8, CX; IMULQ CX, AX` on the outer index that
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* cstage doesn't emit.
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*
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* Cstage walks `n->lhs->type` directly (cmd/w6c/cgen.c N_ASSIGN +
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* N_INDEX lhs) — the typed AST already says the post-inner-index
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* value is *u8, so eff->sub->size = 1 lands naturally. Wwstage now
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* mirrors via indexvaluetnode (already graduated for cgindex in #24).
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*
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* Class A wwstage cgen UNDER. No in-tree consumer surfaced before
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* the fix (selfhost + lib grep is empty for chained-write); the
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* filed-latent sister of #24's surfaced bug. This sentinel is the
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* sole exerciser of the shape.
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*
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* Sentinel per row: in the `probe` body, assert the final element
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* store uses the expected narrow MOV mnemonic, the outer-index
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* scale is absent (esz=1) or matches `MOVQ $<esz>, CX`, and the
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* cstage vs wwstage asm is byte-identical.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include <sys/wait.h>
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static int
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runwait(const char *cmd)
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{
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int rc = system(cmd);
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if (rc == -1) return -1;
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if (WIFEXITED(rc)) return WEXITSTATUS(rc);
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return -1;
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}
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/* `storemov` = expected mnemonic for the trailing `<MOV> AX, (BX)`
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* store at the outer index. `outerscale` = expected esz for the
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* outer index (1 → no IMULQ; 4 → `MOVQ $4, CX; IMULQ`). */
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struct row {
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const char *label;
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const char *src;
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const char *storemov;
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int outerscale;
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};
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static const struct row rows[] = {
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/* The load-bearing case: **u8 chained-write. Sister of 739's
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* **u8 read. esz must drop to 1; MOVB store; no outer scale. */
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{ "chained_u8",
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"fn probe(names: **u8) void = {\n"
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" let i: i32 = 0;\n"
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" let k: u64 = 0u64;\n"
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" names[i][k] = 65u8;\n"
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"};\n"
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"export fn main() i32 = { return 0; };\n",
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"MOVB", 1 },
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/* **i32 — 4-byte store, IMULQ $4 outer scaling, IMULQ $8 inner
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* *i32 stride. */
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{ "chained_i32",
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"fn probe(mat: **i32) void = {\n"
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" let i: i32 = 0;\n"
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" let k: u64 = 0u64;\n"
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" mat[i][k] = 42i32;\n"
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"};\n"
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"export fn main() i32 = { return 0; };\n",
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"MOVL", 4 },
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};
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static int
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slurp(const char *path, char *buf, size_t cap)
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{
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FILE *f = fopen(path, "rb");
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if (!f) return -1;
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size_t n = fread(buf, 1, cap - 1, f);
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fclose(f);
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buf[n] = '\0';
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return (int)n;
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}
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static int
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emit_s(const char *w6c, const struct row *r, int i, char *out_s, size_t cap)
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{
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char src[96], cmd[1024];
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snprintf(src, sizeof src, "/tmp/chwr_%d_%d.ww", getpid(), i);
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snprintf(out_s, cap, "/tmp/chwr_%d_%d_%s.s",
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getpid(), i, w6c[strlen(w6c) - 1] == 'w' ? "ww" : "c");
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FILE *f = fopen(src, "wb");
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if (!f) return -1;
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fputs(r->src, f);
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fclose(f);
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snprintf(cmd, sizeof cmd, "%s -o %s %s 2>/dev/null", w6c, out_s, src);
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int rc = runwait(cmd);
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unlink(src);
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return rc;
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}
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/* Inside `TEXT probe`, the final element store must use the
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* expected narrow MOV mnemonic on `AX, (BX)`. Pre-fix wwstage
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* emitted plain `MOVQ AX, (BX)`. */
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static int
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check_storemov(const char *spath, const struct row *r, const char *stage)
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{
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char buf[1 << 14];
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if (slurp(spath, buf, sizeof buf) < 0) {
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fprintf(stderr, "row[%s][%s]: cannot read %s\n",
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r->label, stage, spath);
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return -1;
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}
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const char *fn = strstr(buf, "TEXT probe");
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if (!fn) {
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fprintf(stderr,
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"row[%s][%s]: no TEXT probe in %s\n",
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r->label, stage, spath);
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return -1;
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}
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const char *ret = strstr(fn, "\tRET\n");
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char needle[64];
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snprintf(needle, sizeof needle, "\t%s\tAX, (BX)\n", r->storemov);
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const char *m = strstr(fn, needle);
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if (!m || (ret && m > ret)) {
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fprintf(stderr,
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"row[%s][%s]: expected `%s AX, (BX)` in probe body\n",
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r->label, stage, r->storemov);
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return -1;
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}
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/* Pre-fix wwstage **u8 write emitted plain `MOVQ AX, (BX)`. For
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* the u8 row that's a wrong-width store — anti-check it is
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* absent. */
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if (r->outerscale == 1) {
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const char *bad = strstr(fn, "\tMOVQ\tAX, (BX)\n");
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if (bad && (!ret || bad < ret)) {
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fprintf(stderr,
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"row[%s][%s]: stray 8-byte `MOVQ AX, (BX)` in "
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"probe body — pre-#27 wrong-width-store regression\n",
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r->label, stage);
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return -1;
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}
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}
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return 0;
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}
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/* Negative: pre-fix wwstage emitted a stray `MOVQ $8, CX; IMULQ CX,
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* AX` for the OUTER index of a **u8 chain (because esz defaulted to
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* 8). For a u8 outer the correct emit is no scaling at all. Assert
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* the count of `MOVQ $8, CX` followed by `IMULQ CX, AX` pairs in the
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* probe body matches the expected inner-only count (= 1 for **T;
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* the inner index of *T elements always scales by 8). */
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static int
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check_inner_scale_only(const char *spath, const struct row *r,
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const char *stage)
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{
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char buf[1 << 14];
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if (slurp(spath, buf, sizeof buf) < 0) return -1;
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const char *fn = strstr(buf, "TEXT probe");
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if (!fn) return -1;
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const char *ret = strstr(fn, "\tRET\n");
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if (!ret) ret = fn + strlen(fn);
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int n_inner = 0, n_outer = 0;
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const char *p = fn;
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while (p < ret) {
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const char *inner = strstr(p, "\tMOVQ\t$8, CX\n");
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if (!inner || inner >= ret) break;
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const char *next = strstr(inner, "\tIMULQ\tCX, AX\n");
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if (!next || next >= ret) { p = inner + 1; continue; }
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n_inner++;
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p = next + 1;
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}
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if (r->outerscale == 1) {
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/* Pre-fix wwstage had two `MOVQ $8, CX; IMULQ` pairs (one
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* for the outer index that shouldn't scale at all). Cstage
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* has one — for the inner *u8 stride only. */
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if (n_inner != 1) {
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fprintf(stderr,
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"row[%s][%s]: expected exactly 1 inner `MOVQ $8, "
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"CX; IMULQ CX, AX` pair (no outer scaling for u8), "
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"got %d\n", r->label, stage, n_inner);
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return -1;
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}
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} else {
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/* For **i32: inner stride is 8 (sizeof *i32), outer scale is
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* 4 (sizeof i32). Assert one `MOVQ $8, CX` for inner and one
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* `MOVQ $4, CX` for outer. */
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p = fn;
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while (p < ret) {
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const char *outer = strstr(p, "\tMOVQ\t$4, CX\n");
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if (!outer || outer >= ret) break;
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const char *next = strstr(outer, "\tIMULQ\tCX, AX\n");
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if (!next || next >= ret) { p = outer + 1; continue; }
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n_outer++;
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p = next + 1;
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}
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if (n_inner != 1 || n_outer != 1) {
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fprintf(stderr,
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"row[%s][%s]: expected 1 inner `MOVQ $8` + 1 outer "
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"`MOVQ $4` IMULQ pair, got inner=%d outer=%d\n",
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r->label, stage, n_inner, n_outer);
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return -1;
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}
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}
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return 0;
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}
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int
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main(void)
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{
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const char *bin = getenv("BIN");
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if (!bin) bin = "out/bin";
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char absbin[512];
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if (bin[0] != '/') {
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char cwd[256];
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if (getcwd(cwd, sizeof cwd) == NULL) return 1;
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snprintf(absbin, sizeof absbin, "%s/%s", cwd, bin);
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bin = absbin;
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}
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char w6c[640], w6c_ww[640];
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snprintf(w6c, sizeof w6c, "%s/w6c", bin);
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snprintf(w6c_ww, sizeof w6c_ww, "%s/w6c_ww", bin);
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int have_ww = (access(w6c_ww, X_OK) == 0);
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int n = (int)(sizeof rows / sizeof rows[0]);
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int total = 0, fail = 0;
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for (int i = 0; i < n; i++) {
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char cs_path[128], ws_path[128];
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if (emit_s(w6c, &rows[i], i, cs_path, sizeof cs_path) != 0) {
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fprintf(stderr,
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"chained_write[cstage][%s]: w6c failed\n",
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rows[i].label);
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fail++; total++; continue;
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}
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total += 2;
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if (check_storemov(cs_path, &rows[i], "cstage") != 0) fail++;
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if (check_inner_scale_only(cs_path, &rows[i], "cstage") != 0)
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fail++;
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if (!have_ww) { unlink(cs_path); continue; }
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if (emit_s(w6c_ww, &rows[i], i, ws_path, sizeof ws_path) != 0) {
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fprintf(stderr,
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"chained_write[wwstage][%s]: w6c_ww failed\n",
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rows[i].label);
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fail++; total++;
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unlink(cs_path); continue;
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}
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total += 2;
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if (check_storemov(ws_path, &rows[i], "wwstage") != 0) fail++;
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if (check_inner_scale_only(ws_path, &rows[i], "wwstage") != 0)
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fail++;
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total++;
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char cmd[512];
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snprintf(cmd, sizeof cmd, "cmp -s %s %s", cs_path, ws_path);
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if (runwait(cmd) != 0) {
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fprintf(stderr,
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"chained_write[%s]: cstage vs wwstage asm differs\n",
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rows[i].label);
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fail++;
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}
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unlink(cs_path); unlink(ws_path);
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}
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if (fail) {
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fprintf(stderr,
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"chained_write: %d/%d fixtures failed\n", fail, total);
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return 1;
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}
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printf("chained_write: %d/%d ok\n", total, total);
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return 0;
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}
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