Hojun-Cho
63332fef50
Shared miscompile in both stages — not a divergence. Bootstrap byte-id
passed throughout because both stages emitted the same wrong asm. Both
the C cgen (cmd/w6c/cgen.c TK_SLASH/TK_PERCENT) and the ww cgen
(selfhost/cmd/wcc/cgenexpr.ww) prepped IDIVQ with `MOVQ $0, DX`, which
is the unsigned 128-bit dividend shape. For a negative RAX, the CPU
then divides 2^64 + (-RAX) by the divisor — unsigned wraparound, not
signed division. Surfaced via lib/time/add() needing the verbatim Hare
signed-%-normalisation in ref/hare/time/arithm.ha.
Fix: emit CQO (sign-extend RAX into RDX:RAX, REX.W 99) on the signed
arm; keep MOVQ $0, DX on the unsigned arm where the DIVQ-vs-IDIVQ
dispatch was already correct. Since both stages always emit 64-bit
IDIVQ regardless of source width, a single CQO suffices for
i64/i32/i16/i8 — the dividend already lives in RAX sign-extended. No
CDQ/CWTL/CBTW needed.
Symmetric stages (rule 10): both stages were broken identically; both
get the same surgical fix. Adds A_CQO to each assembler's opcode set:
cstage in cmd/w6c/6.out.h + cmd/w6c/txt.c + cmd/w6a/{parse,asm}.c;
wwstage in selfhost/cmd/w6a/{types,parse,asm}.ww.
Class B (shared miscompile) — new in the session's polarity catalog.
Bootstrap byte-id is useless for catching it; semantic 9xx runtime
tests are the right shape. test/wcc/978_intdiv_signed.c covers 27 rows
× 2 drivers = 54 fixtures across {i8,i16,i32,i64,u8,u16,u32,u64} ×
{/, %} with width-boundary minima (INT8_MIN, INT16_MIN, INT32_MIN,
INT64_MIN/2) and high-bit-set unsigned anchors. INT64_MIN is spelled
(-INT64_MAX) - 1 per task #17 (wwstage NEGQ-over-imm drops digits on
-9223372036854775808i64); that literal-cgen bug is unrelated to this
fix.
Two known compound-assign workarounds at cmd/w6c/cgen.c:3765
(TK_SLASHEQ IDENT-local) and :3549 (TK_SLASHEQ/TK_PERCENTEQ
deref-compound) remain in tree; both depend on the assembler having
CQO, so they revert in a follow-up commit citing this one.
119 lines
2.6 KiB
C
119 lines
2.6 KiB
C
/*
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* 6.out.h — amd64 instruction enum + register names. Mirrors the
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* Plan 9 6c shape (cmd/6c/6.out.h) but trimmed to the subset that
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* w6c emits and w6a consumes in this bootstrap. Each new opcode added
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* here must also gain encoding support in cmd/w6a/asm.c.
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*/
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#ifndef SIX_OUT_H
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#define SIX_OUT_H
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/* registers — Plan 9 names; lowercase = 8-bit, etc. We use 64-bit. */
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enum {
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D_NONE = 0,
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/* general purpose 64-bit */
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D_AX, D_CX, D_DX, D_BX,
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D_SP, D_BP, D_SI, D_DI,
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D_R8, D_R9, D_R10, D_R11,
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D_R12, D_R13, D_R14, D_R15,
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/* SSE/XMM 64-bit float regs */
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D_X0, D_X1, D_X2, D_X3,
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D_X4, D_X5, D_X6, D_X7,
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D_X8, D_X9, D_X10, D_X11,
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D_X12, D_X13, D_X14, D_X15,
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/* pseudo regs (Plan 9) */
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D_PSP, /* SP pseudo (frame-relative) */
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D_PFP, /* FP pseudo (incoming args) */
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D_PSB, /* SB pseudo (static base) */
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/* operand kinds; not registers but share the slot */
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D_CONST, /* $N immediate */
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D_BRANCH, /* label reference */
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D_EXTERN, /* external symbol */
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D_INDIR /* offset(reg) memory */
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};
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/* opcodes — the small set we currently emit & encode */
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enum {
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A_NOP = 0,
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A_TEXT,
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A_DATA,
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A_DATAW, /* writable DATA: lands in .data (RW) instead of .text */
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A_DATAR, /* reloc-only: patch a 64-bit slot in .data with a
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* symbol's runtime VA. Pairs with a prior DATAW
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* that left zero placeholder bytes. */
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A_GLOBL,
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A_END,
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A_MOVQ,
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A_MOVL,
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A_MOVW,
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A_MOVB,
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A_MOVZBQ, /* movzx r64, r/m8 — byte zero-extended */
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A_MOVZWQ, /* movzx r64, r/m16 — word zero-extended */
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A_MOVSXD, /* movsxd r64, r/m32 — i32 sign-extended */
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A_MOVSWQ, /* movsx r64, r/m16 — i16 sign-extended */
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A_MOVSBQ, /* movsx r64, r/m8 — i8 sign-extended */
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/* SSE2 scalar double-precision float */
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A_MOVSD, /* xmm/m → xmm and xmm → m */
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A_ADDSD,
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A_SUBSD,
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A_MULSD,
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A_DIVSD,
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A_UCOMISD,
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A_CVTTSD2SI, /* truncate f64 → i64 */
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A_CVTSI2SD, /* convert i64 → f64 */
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/* SSE scalar single-precision float (f32). Same xmm regs. */
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A_MOVSS,
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A_ADDSS,
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A_SUBSS,
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A_MULSS,
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A_DIVSS,
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A_UCOMISS,
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A_CVTTSS2SI,
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A_CVTSI2SS,
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A_CVTSD2SS, /* f64 → f32 truncate */
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A_CVTSS2SD, /* f32 → f64 widen */
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A_ADDQ,
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A_SUBQ,
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A_IMULQ,
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A_IDIVQ,
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A_DIVQ, /* unsigned 64-bit divide; sibling of IDIVQ */
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A_CQO, /* sign-extend RAX into RDX:RAX; the signed-division
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* prep that pairs with IDIVQ (DIVQ pairs with a
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* MOVQ $0, DX zero-fill). */
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A_NEGQ,
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A_NOTQ,
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A_ANDQ,
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A_ORQ,
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A_XORQ,
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A_SHLQ,
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A_SHRQ,
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A_CMPQ,
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A_PUSHQ,
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A_POPQ,
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A_LEAQ,
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A_CALL,
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A_RET,
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A_JMP,
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A_JE, A_JNE,
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A_JL, A_JLE, A_JG, A_JGE,
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A_JB, A_JBE, A_JA, A_JAE,
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A_JZ, A_JNZ,
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A_SYSCALL,
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A_LAST
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};
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const char *anames(int); /* opcode -> mnemonic */
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const char *rnames(int); /* register -> name */
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#endif
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