Files
ww/selfhost/cmd/w6l/pass.ww
Hojun-Cho 1ac9980f7e selfhost: mirror writable .data + R_X86_64_64 across the wwstage
Bring the wwstage toolchain to parity with C-side DATAW / DATAR /
.data / .rela.data support. With this, w6c_ww + w6a_ww + w6l_ww can
compile, assemble and link `let g: str = "lit";` (and the scalar /
str / slice / struct globals that landed earlier) end-to-end, with
output that's byte-identical to the C-side pipeline.

w6a (types.ww / parse.ww / asm.ww / obj.ww):
  - A_DATAW + A_DATAR opcodes; parser learns `name+disp(SB)`;
    A_DATAR records an R_X86_64_64 reloc in .data via the new
    addrelocdata helper; areloc gains a `section` flag and asym
    an `isdata` flag; obj.ww splits relocs into .rela.text /
    .rela.data, emits .data PROGBITS + .rela.data conditionally,
    and shuffles section indices the same way cmd/w6a/obj.c does
    so byte output stays identical when no DATAW/DATAR are used.

w6l (sym.ww / obj.ww / pass.ww / out.ww / dynout.ww / main.ww):
  - lrel grows `section`; lsym grows `indata`; lobj tracks
    dataoff / datasize; lnk grows combined .data buffer;
  - obj.ww loads .data and .rela.data, registers data symbols
    with indata=1 and val shifted by the input's data_off, and
    the archive scanner includes both .text and .data globals;
  - pass.ww adds R_X86_64_64 (patch 8 bytes in .text or .data
    with sym_va + addend); relocate's signature becomes
    (textva, datava);
  - out.ww emits a second PT_LOAD (R+W) when datalen > 0, with
    .data at the page-aligned offset after .text;
  - dynout.ww refuses .data + -l/-L cleanly (matches the C-side
    error message);
  - main.ww computes text_va / data_va and passes both to
    relocate.

wcc cgen (cgen.ww / cgendecl.ww):
  - letpreintern walks top-level str-lets and interns the strlit
    BEFORE emitdatasection emits its DATA row, so emitletdataw
    can later look up the same label;
  - emitletdataw's 16B branch detects non-empty strlit init and
    emits the 8-zero + 8-LE-len DATAW plus a DATAR slot+0,strlit
    reloc, mirroring cmd/w6c/cgen.c.

Verified: `wwdump_ww -c` byte-matches `w6c` on a `let g: str =
"hello world\n";` fixture; `w6a_ww` and `w6l_ww` produce a
binary byte-identical to the C-side pipeline that runs and
prints "hello world". Bootstrap fixed-point holds (ww2 == ww3 ==
ww4), 26/26 tests green.
2026-05-12 13:03:03 +09:00

133 lines
3.5 KiB
Plaintext

// selfhost/cmd/w6l/pass.ww — port of cmd/w6l/pass.c.
//
// Resolution + relocation. l_resolve flags every undefined symbol
// referenced by a relocation, and promotes those provided by some
// loaded .so to "dynamic" with a freshly-assigned PLT slot.
// l_relocate walks the rel list and patches the .text bytes in place
// once the final virtual base is known. Dynamic refs are deferred:
// their site is patched later in dynout, once the PLT vaddr is known.
//
// Supported relocation kinds: PC32 (=2), PLT32 (=4); both are 32-bit
// PC-relative displacements (PLT32 == PC32 for static).
use os;
use sym;
use dyn;
def R_X86_64_64: i32 = 1;
def R_X86_64_PC32: i32 = 2;
def R_X86_64_PLT32: i32 = 4;
export fn resolve(l: *lnk) i32 = {
// Initialise dynamic-linking sentinels. amalloc zeroes, so
// isdyn/dynlib start clean — but pltidx and dynsymidx
// must be -1, not 0.
let si: *lsym = l.syms;
for (si != nil) {
si.pltidx = -1;
si.dynsymidx = -1;
si = si.snext;
};
// Promote each undefined sym that some lso exports to dynamic
// and hand it a PLT slot. Iteration order over the relocation
// list determines slot numbering and is stable across runs.
let r: *lrel = l.rels;
for (r != nil) {
if (r.sym != nil) {
if (r.sym.defined == 0) {
if (r.sym.isdyn == 0) {
let so: *lso = l.sos;
for (so != nil) {
if (soprovides(so, r.sym.name) != 0) {
r.sym.isdyn = 1;
r.sym.dynlib = so;
r.sym.pltidx = l.dynn;
l.dynn += 1;
so = nil; // break
} else {
so = so.sonext;
};
};
};
};
};
r = r.rnext;
};
// What remains undefined truly is undefined.
let r2: *lrel = l.rels;
for (r2 != nil) {
if (r2.sym != nil) {
if (r2.sym.defined == 0) {
if (r2.sym.isdyn == 0) {
os.write(2, "w6l: undefined reference to '".ptr, 28u64);
let nm: str = r2.sym.name;
os.write(2, nm.ptr, nm.len: u64);
os.write(2, "'\n".ptr, 2u64);
l.errs += 1;
};
};
};
r2 = r2.rnext;
};
return l.errs;
};
fn patchu32(p: *u8, v: u32) void = {
p[0] = (v & 255u32): u8;
p[1] = ((v >> 8u32) & 255u32): u8;
p[2] = ((v >> 16u32) & 255u32): u8;
p[3] = ((v >> 24u32) & 255u32): u8;
};
fn patchu64(p: *u8, v: u64) void = {
let i: i32 = 0;
for (i < 8) {
p[i] = ((v >> (i: u64 * 8u64)) & 255u64): u8;
i += 1;
};
};
export fn relocate(l: *lnk, textva: u64, datava: u64) i32 = {
let r: *lrel = l.rels;
for (r != nil) {
if (r.sym != nil) {
// Dynamic refs are patched later in dynout once the
// PLT vaddr is known.
if (r.sym.isdyn != 0) {
r = r.rnext;
continue;
};
if (r.sym.defined != 0) {
let symva: u64 = textva + r.sym.val;
if (r.sym.indata != 0) { symva = datava + r.sym.val; };
let k: i32 = r.kind;
if (k == R_X86_64_PC32) {
let site: u64 = textva + r.off;
let rel: i64 = (symva: i64 - site: i64) + r.addend;
patchu32(l.text + r.off, rel: u32);
} else { if (k == R_X86_64_PLT32) {
let site: u64 = textva + r.off;
let rel: i64 = (symva: i64 - site: i64) + r.addend;
patchu32(l.text + r.off, rel: u32);
} else { if (k == R_X86_64_64) {
// Absolute 64-bit. Currently used only
// for DATAR slots in .data.
let v: u64 = (symva: i64 + r.addend): u64;
if (r.section == 1) {
patchu64(l.data + r.off, v);
} else {
patchu64(l.text + r.off, v);
};
} else {
os.write(2, "w6l: unsupported reloc kind\n".ptr, 27u64);
l.errs += 1;
};};};
};
};
r = r.rnext;
};
return l.errs;
};