Hojun-Cho
7db30bf609
Three more value-observable behavior families ported from the C corpus to in-language @test, routed by the ratified observability rule (value -> test/lang @test; process-outcome stays in runww). Additive: the .c sources keep running in $(TESTS), so no byte-id coverage is removed -- de-dup is deferred to fold 6 (task #12). 906_callret_unsigned_arith -> callret_unsigned_test: call-result unsigned opcode select keyed by callee return type (#168, the N_CALL twin of gunsigned's module-global #134); operands flow through real calls so the return-type arm is exercised, not N_IDENT. 912_sar_shr -> sar_shr_test: signed >> / >>= must emit SAR not SHR (#136); asserts the i64/i32 value directly, dropping the C 8-bit exit-code encoding. 793_widen_pad_zero -> widen_pad_test: widening a narrow value into a wider tagged slot zeroes the high pad words (#227).
85 lines
2.7 KiB
Plaintext
85 lines
2.7 KiB
Plaintext
// sar_shr_test — a SIGNED right-shift (both plain `>>` and compound `>>=`)
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// must emit SAR (arithmetic, sign-fills the MSB), not SHR (logical, zero-fill),
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// migrated from test/wcc/912_sar_shr_run.c (#136). Pre-fix BOTH stages emitted
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// SHRQ for signed RSHIFT (A_SARQ was absent from the w6a opcode table), so
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// `let i: i32 = -200; i >>= 2;` produced 0x3FFFFFCE (1073741774) instead of
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// -50 — cs==ww held, so byte-id was GREEN while the runtime was wrong. The C
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// .c keeps the .s byte-id net; this file pins the RUNTIME semantics directly,
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// dropping the C original's 8-bit exit-code encoding (assert the i64/i32 value
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// in-language — the whole point of the @test model).
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//
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// Unlike gunsigned/idxarg, the bug lives in the shift codegen itself, not in
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// how the operand is sourced, so indexing a row's operand and then shifting
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// STILL exercises the shift site — a row-loop is appropriate. The VALUE (neg
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// vs pos) is the data dimension and loops; the (type, operator) SHAPE selects
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// distinct shift sites (i32 vs i64; cgbin `>>` vs compound `>>=`), so it is one
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// @test fn per shape over a shared row table. Negatives discriminate SAR from
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// SHR; the positive row is a no-regression control (SAR == SHR on positives).
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package sar_shr_test;
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// One shift row: x >> sh (or x >>= sh) must equal want. Each consuming @test
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// fixes the operand TYPE and OPERATOR; the rows vary only sign/magnitude.
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type shrow = struct {
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x: i64,
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sh: i64,
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want: i64,
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};
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let rows: [3]shrow = [
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shrow { x = -200i64, sh = 2i64, want = -50i64 },
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shrow { x = -8i64, sh = 1i64, want = -4i64 },
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shrow { x = 200i64, sh = 2i64, want = 50i64 },
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];
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@test fn shift_i64_binop() void = {
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let i: i32 = 0;
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for (i < len(rows)) {
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assert(rows[i].x >> rows[i].sh == rows[i].want);
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i += 1;
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};
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};
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@test fn shift_i64_compound() void = {
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let i: i32 = 0;
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for (i < len(rows)) {
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let v: i64 = rows[i].x;
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v >>= rows[i].sh;
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assert(v == rows[i].want);
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i += 1;
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};
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};
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@test fn shift_i32_binop() void = {
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let i: i32 = 0;
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for (i < len(rows)) {
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let x: i32 = rows[i].x: i32;
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let r: i32 = x >> (rows[i].sh: i32);
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assert(r == rows[i].want: i32);
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i += 1;
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};
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};
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@test fn shift_i32_compound() void = {
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let i: i32 = 0;
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for (i < len(rows)) {
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let v: i32 = rows[i].x: i32;
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v >>= rows[i].sh: i32;
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assert(v == rows[i].want: i32);
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i += 1;
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};
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};
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@test fn shift_unsigned_ctl() void = {
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// u32 control: 200u32 >> 2 == 50 — SHRQ unchanged by the fix.
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let a: u32 = 200u32;
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a >>= 2u32;
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assert(a == 50u32);
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// u64 high-bit control: the fix must NOT make unsigned use SAR. A
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// logical SHRQ of 0x8000..0 >> 1 == 0x4000..0; an over-broad SARQ would
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// sign-fill the set MSB → 0xC000..0.
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let b: u64 = 0x8000000000000000u64;
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assert(b >> 1u64 == 0x4000000000000000u64);
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};
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