UCOMISD/UCOMISS set PF=ZF=CF=1 on unordered (a NaN operand). The old arms keyed on ZF/CF only, so 4 of the 6 relops mishandled NaN: `nan != nan` was false (JNE keys on ZF=0), `nan == nan` was true, and `<`/`<=` (JB/JBE) fired on the unordered CF=1. IEEE-754: any relop with a NaN operand is unordered — `!=` true, the rest false. `!=` now jumps to true on JNE OR JP; `==`/`<`/`<=` jump to false on JP before the ordered Jcc. `>`/`>=` (JA/JAE) are LEFT UNCHANGED: they require CF=0, which an unordered UCOMISD never produces, so they already reject NaN correctly. Adding a PF guard there would only churn their .s (an extra JP on every >/>= float compare) for no correctness gain, so their arm stays byte-identical to the pre-#97 single template. Bundles the cgen fix with JP-mnemonic support in both assemblers (w6c enum/printer + w6a/w6a_ww parse+encode, 0F 8A). They can't split: the cgen emits JP, which has no encoding without the assembler change, so a cgen-only commit would not build. JP is the only PF-sensitive jump on amd64 — there is no alternative instruction.
222 lines
4.9 KiB
Plaintext
222 lines
4.9 KiB
Plaintext
// selfhost/cmd/w6a/opcodes.ww — types + constants shared across the
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// w6a port. Mirrors cmd/w6a/a.h and cmd/w6c/6.out.h.
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package w6a;
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// ---- registers + operand kinds (from 6.out.h) -------------------------
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// These must stay numerically aligned with the C enum so that ww-cgen
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// output (which reads them via `D_AX(SB)` etc.) lands on the same
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// integers when read by ww-w6a.
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def D_NONE: i32 = 0;
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def D_AX: i32 = 1;
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def D_CX: i32 = 2;
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def D_DX: i32 = 3;
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def D_BX: i32 = 4;
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def D_SP: i32 = 5;
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def D_BP: i32 = 6;
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def D_SI: i32 = 7;
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def D_DI: i32 = 8;
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def D_R8: i32 = 9;
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def D_R9: i32 = 10;
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def D_R10: i32 = 11;
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def D_R11: i32 = 12;
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def D_R12: i32 = 13;
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def D_R13: i32 = 14;
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def D_R14: i32 = 15;
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def D_R15: i32 = 16;
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def D_X0: i32 = 17;
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def D_X1: i32 = 18;
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def D_X2: i32 = 19;
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def D_X3: i32 = 20;
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def D_X4: i32 = 21;
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def D_X5: i32 = 22;
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def D_X6: i32 = 23;
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def D_X7: i32 = 24;
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def D_X8: i32 = 25;
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def D_X9: i32 = 26;
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def D_X10: i32 = 27;
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def D_X11: i32 = 28;
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def D_X12: i32 = 29;
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def D_X13: i32 = 30;
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def D_X14: i32 = 31;
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def D_X15: i32 = 32;
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def D_PSP: i32 = 33;
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def D_PFP: i32 = 34;
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def D_PSB: i32 = 35;
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def D_CONST: i32 = 36;
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def D_BRANCH: i32 = 37;
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def D_EXTERN: i32 = 38;
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def D_INDIR: i32 = 39;
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// ---- opcodes ----------------------------------------------------------
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def A_NOP: i32 = 0;
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def A_TEXT: i32 = 1;
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def A_DATA: i32 = 2;
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def A_GLOBL: i32 = 3;
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def A_END: i32 = 4;
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def A_MOVQ: i32 = 5;
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def A_MOVL: i32 = 6;
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def A_MOVB: i32 = 7;
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def A_MOVZBQ: i32 = 8;
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def A_MOVSXD: i32 = 9;
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def A_MOVW: i32 = 62;
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def A_MOVZWQ: i32 = 63;
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def A_MOVSWQ: i32 = 64;
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def A_MOVSBQ: i32 = 65;
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def A_MOVSD: i32 = 10;
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def A_ADDSD: i32 = 11;
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def A_SUBSD: i32 = 12;
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def A_MULSD: i32 = 13;
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def A_DIVSD: i32 = 14;
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def A_UCOMISD: i32 = 15;
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def A_CVTTSD2SI: i32 = 16;
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def A_CVTSI2SD: i32 = 17;
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def A_MOVSS: i32 = 18;
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def A_ADDSS: i32 = 19;
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def A_SUBSS: i32 = 20;
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def A_MULSS: i32 = 21;
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def A_DIVSS: i32 = 22;
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def A_UCOMISS: i32 = 23;
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def A_CVTTSS2SI: i32 = 24;
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def A_CVTSI2SS: i32 = 25;
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def A_CVTSD2SS: i32 = 26;
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def A_CVTSS2SD: i32 = 27;
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def A_ADDQ: i32 = 28;
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def A_SUBQ: i32 = 29;
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def A_IMULQ: i32 = 30;
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def A_IDIVQ: i32 = 31;
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def A_DIVQ: i32 = 32;
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def A_NEGQ: i32 = 33;
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def A_NOTQ: i32 = 34;
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def A_ANDQ: i32 = 35;
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def A_ORQ: i32 = 36;
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def A_XORQ: i32 = 37;
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def A_SHLQ: i32 = 38;
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def A_SHRQ: i32 = 39;
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def A_CMPQ: i32 = 40;
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def A_PUSHQ: i32 = 41;
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def A_POPQ: i32 = 42;
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def A_LEAQ: i32 = 43;
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def A_CALL: i32 = 44;
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def A_RET: i32 = 45;
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def A_JMP: i32 = 46;
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def A_JE: i32 = 47;
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def A_JNE: i32 = 48;
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def A_JL: i32 = 49;
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def A_JLE: i32 = 50;
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def A_JG: i32 = 51;
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def A_JGE: i32 = 52;
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def A_JB: i32 = 53;
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def A_JBE: i32 = 54;
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def A_JA: i32 = 55;
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def A_JAE: i32 = 56;
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def A_JZ: i32 = 57;
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def A_JNZ: i32 = 58;
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// 67 (next free above A_CQO=66): appended so the existing A_MOV*/
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// A_SYSCALL/A_DATAW/A_DATAR/A_CQO numbers stay put. Jump on
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// parity (PF=1): UCOMISD unordered (#97).
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def A_JP: i32 = 67;
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def A_SYSCALL: i32 = 59;
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// Writable data + reloc-only data. Mirror cmd/w6c/6.out.h.
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// A_DATAW: bytes land in .data (RW) instead of .text.
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// A_DATAR: record an R_X86_64_64 reloc at a .data slot, patched
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// to a target symbol's runtime VA at link time.
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def A_DATAW: i32 = 60;
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def A_DATAR: i32 = 61;
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// REX.W 99 — sign-extend RAX into RDX:RAX. Pairs with IDIVQ for
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// signed division; pendant to the MOVQ $0, DX zero-fill that pairs
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// with DIVQ.
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def A_CQO: i32 = 66;
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// ---- structs (mirror cmd/w6a/a.h) --------------------------------------
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type aoperand = struct {
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atype: i32, // D_NONE / D_AX..D_R15 / D_CONST / D_INDIR / D_EXTERN / D_BRANCH
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reg: i32,
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offset: i64,
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asym: str,
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};
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// `from` and `to` are pointer-to-aoperand (rather than embedded).
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// The C cgen doesn't support chained-dot through embedded value
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// fields, so allocating each operand once per prog lets us write
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// `p.to.atype` directly.
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type aprog = struct {
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as_: i32,
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from: *aoperand,
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to: *aoperand,
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line: i32,
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label: str,
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link: *aprog,
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bytes: *u8, // payload for A_DATA
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nbytes: u64,
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};
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type asym = struct {
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name: str,
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defined: i32,
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istext: i32,
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isdata: i32, // mutually exclusive with istext; DATAW symbols
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isglobal: i32,
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addr: u64, // offset within its section (.text or .data)
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idx: i32,
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snext: *asym,
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};
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type areloc = struct {
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off: u64,
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section: i32, // 0 = .text, 1 = .data
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kind: i32,
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asy: *asym,
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addend: i64,
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rnext: *areloc,
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};
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type afixup = struct {
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off: u64, // where the rel32 lands in .text
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label: str,
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fnext: *afixup,
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};
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type asm_ = struct {
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file: str,
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src: *u8,
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srclen: u64,
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pos: u64,
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line: i32,
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head: *aprog,
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tail: *aprog,
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text: *u8,
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textcap: u64,
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textlen: u64,
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// Writable .data. Empty unless any DATAW directive was seen;
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// obj.ww emits the extra section conditionally so .o output
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// stays byte-identical for inputs that don't use DATAW (test
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// 991 byte-diff invariant).
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data: *u8,
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datacap: u64,
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datalen: u64,
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syms: *asym,
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relocs: *areloc,
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fixups: *afixup,
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errs: i32,
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};
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