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cgen: f64 compare consults parity flag for NaN, 4 relops (both stages, #97)

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UCOMISD/UCOMISS set PF=ZF=CF=1 on unordered (a NaN operand). The old
arms keyed on ZF/CF only, so 4 of the 6 relops mishandled NaN:
`nan != nan` was false (JNE keys on ZF=0), `nan == nan` was true, and
`<`/`<=` (JB/JBE) fired on the unordered CF=1. IEEE-754: any relop
with a NaN operand is unordered — `!=` true, the rest false. `!=` now
jumps to true on JNE OR JP; `==`/`<`/`<=` jump to false on JP before
the ordered Jcc.

`>`/`>=` (JA/JAE) are LEFT UNCHANGED: they require CF=0, which an
unordered UCOMISD never produces, so they already reject NaN
correctly. Adding a PF guard there would only churn their .s (an extra
JP on every >/>= float compare) for no correctness gain, so their arm
stays byte-identical to the pre-#97 single template.

Bundles the cgen fix with JP-mnemonic support in both assemblers
(w6c enum/printer + w6a/w6a_ww parse+encode, 0F 8A). They can't split:
the cgen emits JP, which has no encoding without the assembler change,
so a cgen-only commit would not build. JP is the only PF-sensitive
jump on amd64 — there is no alternative instruction.
This commit is contained in:
Hojun-Cho
2026-05-25 12:40:23 +09:00
parent 2f2a73bd41
commit fa136d0b88
12 changed files with 214 additions and 44 deletions
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selfhost/cmd/w6a/parse.ww
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@@ -90,6 +90,7 @@ fn opcodelookup(p: *u8, n: u64) i32 = {
if (streqlit(p, n, "JAE")) { return A_JAE; };
if (streqlit(p, n, "JZ")) { return A_JZ; };
if (streqlit(p, n, "JNZ")) { return A_JNZ; };
if (streqlit(p, n, "JP")) { return A_JP; };
if (streqlit(p, n, "SYSCALL")) { return A_SYSCALL; };
if (streqlit(p, n, "TEXT")) { return A_TEXT; };
if (streqlit(p, n, "DATA")) { return A_DATA; };