cgen: f64 compare consults parity flag for NaN, 4 relops (both stages, #97)

UCOMISD/UCOMISS set PF=ZF=CF=1 on unordered (a NaN operand). The old
arms keyed on ZF/CF only, so 4 of the 6 relops mishandled NaN:
`nan != nan` was false (JNE keys on ZF=0), `nan == nan` was true, and
`<`/`<=` (JB/JBE) fired on the unordered CF=1. IEEE-754: any relop
with a NaN operand is unordered — `!=` true, the rest false. `!=` now
jumps to true on JNE OR JP; `==`/`<`/`<=` jump to false on JP before
the ordered Jcc.

`>`/`>=` (JA/JAE) are LEFT UNCHANGED: they require CF=0, which an
unordered UCOMISD never produces, so they already reject NaN
correctly. Adding a PF guard there would only churn their .s (an extra
JP on every >/>= float compare) for no correctness gain, so their arm
stays byte-identical to the pre-#97 single template.

Bundles the cgen fix with JP-mnemonic support in both assemblers
(w6c enum/printer + w6a/w6a_ww parse+encode, 0F 8A). They can't split:
the cgen emits JP, which has no encoding without the assembler change,
so a cgen-only commit would not build. JP is the only PF-sensitive
jump on amd64 — there is no alternative instruction.

cmd/w6a/parse.c

@@ -119,6 +119,7 @@ opcode_lookup(const char *m)
 		{ "JB",   A_JB   },{ "JBE",  A_JBE  },
 		{ "JA",   A_JA   },{ "JAE",  A_JAE  },
 		{ "JZ",   A_JZ   },{ "JNZ",  A_JNZ  },
+		{ "JP",   A_JP   },
 		{ "SYSCALL", A_SYSCALL },
 		{ "TEXT", A_TEXT },
 		{ "DATA", A_DATA },