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w6c+w6a+selfhost+lib: cgen+asm bugs surfaced by hash modules

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Seven fixes across the toolchain, plus three new lib/hash modules
(adler32, crc16, crc32) that surfaced them.

  1. `~x` on u8/u16/u32 left the upper bits set: NOTQ inverts the
     whole 64-bit register and nothing trimmed it back to type
     width, so a returned `u16` would compare 64-bit against a
     typed literal and disagree. Both stages now mask after NOTQ
     for narrow unsigned: AND $0xFF/0xFFFF for u8/u16, MOVL r,r for
     u32 (ANDQ $0xFFFFFFFF sign-extends imm32 and is a no-op).
     Signed narrows stay sign-extended and need no fix-up. See
     cmd/w6c/cgen.c N_UN TK_TILDE and selfhost cgenexpr.ww cgun
     TK_TILDE with new nodeprimwidth helper.

  2. w6a had no D_CONST immediate path for ANDQ / ORQ. cgen would
     emit `ANDQ $65535, AX` and the rr encoder silently wrote
     `21 /r` with garbage reg fields — the mask never happened.
     Added `81 /4` (AND) and `81 /1` (OR) imm32 paths in both
     cstage and selfhost w6a. The ~width fix above depends on this.

  3. `s: []u8` cast as a direct fn argument produced a 0-length
     slice. cgexpr for N_CAST left (AX=ptr, BX=len) from the str
     source but never set CX (cap), and the arg-push fallback only
     pushed AX. cgcast now synthesises CX=BX when target is slice
     and source is str; node_isslice / arg-push recognise
     cast-to-slice and emit the full (cap, len, ptr) triple. Both
     stages.

  4. `*[N]T` element-store used 8-byte stride + MOVQ regardless of
     T's width. Indexing `buf: *[4]u16` would step 8 bytes and
     write 8 bytes per element. Added idx_eff (drills *[N]T → T)
     in cstage and the matching pointer-array drill in selfhost
     elemsizeof. Also added MOVW / MOVZWQ / MOVSWQ to w6c, w6a,
     and selfhost mirrors so 2-byte element stores/loads use the
     right opcode (was falling through to MOVQ and trailing 6 bytes
     into the next slot).

  5. Slicing a top-level fixed array (`g[0:n]` where `g: [N]T` is
     a global) computed the base from BP instead of the symbol —
     localfind returned 0 and the cgen treated it as a local at
     offset 0. Both N_SLICE-as-expression (cgslice) and N_SLICE-
     as-call-arg paths now check let_islet / letvartnode and emit
     LEAQ name(SB) when the base is a global array (or MOVQ
     name(SB) for a global slice/pointer base). Both stages.

  6. Top-level `let arr: [N]T = [v0, v1, ...]` link-failed on
     cstage — emit_lets bailed when it saw N_ARRLIT init on an
     array type, and the sz==8 scalar path then misemitted any
     8-byte-sized array (e.g. [4]u16, [8]u8) as a single quad.
     emit_lets now walks N_ARRLIT, evaluates each element as an
     int/rune/bool/nil literal, packs per-element bytes
     little-endian, and honours the trailing `...` repeat marker.
     Selfhost already handled the literal-init path; fixed the
     parallel sz==8 duplicate-DATAW emit on its side (the array
     and the scalar paths both fired, last write winning at link
     but the duplicate broke cross-stage byte-identicality on user
     code with this shape).

  7. w6a's per-line input buffer was a 1KB stack `char buf[1024]`.
     A `DATAW` for a [256]u16 emits ~2080 bytes on one line, which
     truncated mid-escape; the assembler then re-parsed the
     remaining tail as garbage opcodes ("unknown opcode"). Bumped
     cstage w6a to a 32K static buffer (selfhost w6a already
     allocated per-line via amalloc).

  lib: lib/hash/adler32, lib/hash/crc16, lib/hash/crc32 — pure
  buffer-subset shape (matching lib/hash/fnv), with per-module
  *_test.ww runnable via `ww test lib/hash/<name>`. Adler-32 plus
  CRC-16 (CCITT/CMDA2000/DECT/ANSI) and CRC-32 (IEEE/Castagnoli/
  Koopman) cover Hare's reference vectors bit-for-bit. Wired into
  test/wcc/900_stdlib.c. .gitignore: lib/**/*.s,*.o so `ww test`
  droppings stay untracked.

`make test` (26/26), `make bootstrap` (ww2≡ww3≡ww4), and per-module
`ww test` all pass. cgen output is byte-identical across cstage and
selfhost for every repro that previously diverged.
This commit is contained in:
Hojun-Cho
2026-05-13 14:26:18 +09:00
parent b05968c7f4
commit cbcc0167ae
22 changed files with 1242 additions and 59 deletions
Download Patch File Download Diff File Expand all files Collapse all files

101
selfhost/cmd/wcc/cgenexpr.ww
View File

@@ -357,6 +357,23 @@ fn cgcast(c: *cgen, n: *node) void = {
if (dstf32) { dstfk = 1; }
else { if (dstf64) { dstfk = 2; }; };
cgexpr(c, n.lhs);
// str → []T: cgexpr left (AX=ptr, BX=len). Slice register
// convention is (AX=ptr, BX=len, CX=cap); synthesise cap = len
// so downstream arg-push / let-init paths see the canonical
// triple. Detect via dst-is-slice + src-ident's local-tnode
// being str (the common shape; non-ident sources rare).
if (isslicetype(c, n.rhs)) {
let srcstr: bool = false;
if (n.lhs != nil) {
if (n.lhs.kind == nkind.N_IDENT) {
let lc: *local = localfindnode(c, n.lhs.str);
if (lc != nil) {
if (isstrtype(c, lc.tnode)) { srcstr = true; };
};
};
};
if (srcstr) { emitline("\tMOVQ\tBX, CX\n"); };
};
// 0=int, 1=f32, 2=f64. CVT picks one direction per combo;
// same-kind casts (int↔int with widening differences,
// f64→f64 etc.) stay no-ops at the asm level, matching the
@@ -632,11 +649,15 @@ fn cgindex(c: *cgen, n: *node) void = {
return;
};
if (esz == 1) { emitline("\tMOVZBQ\t(BX), AX\n"); }
else { if (esz == 2) {
if (signed_elem) { emitline("\tMOVSWQ\t(BX), AX\n"); }
else { emitline("\tMOVZWQ\t(BX), AX\n"); };
}
else { if (esz == 4) {
if (signed_elem) { emitline("\tMOVSXD\t(BX), AX\n"); }
else { emitline("\tMOVL\t(BX), AX\n"); };
}
else { emitline("\tMOVQ\t(BX), AX\n"); };};
else { emitline("\tMOVQ\t(BX), AX\n"); };};};
return;
};
if (baselocal != nil) {
@@ -675,11 +696,15 @@ fn cgindex(c: *cgen, n: *node) void = {
return;
};
if (esz == 1) { emitline("\tMOVZBQ\t(BX), AX\n"); }
else { if (esz == 2) {
if (signed_elem) { emitline("\tMOVSWQ\t(BX), AX\n"); }
else { emitline("\tMOVZWQ\t(BX), AX\n"); };
}
else { if (esz == 4) {
if (signed_elem) { emitline("\tMOVSXD\t(BX), AX\n"); }
else { emitline("\tMOVL\t(BX), AX\n"); };
}
else { emitline("\tMOVQ\t(BX), AX\n"); };};
else { emitline("\tMOVQ\t(BX), AX\n"); };};};
return;
};
// Generic fallback when base isn't a plain ident.
@@ -706,11 +731,15 @@ fn cgindex(c: *cgen, n: *node) void = {
return;
};
if (esz == 1) { emitline("\tMOVZBQ\t(AX), AX\n"); }
else { if (esz == 2) {
if (signed_elem) { emitline("\tMOVSWQ\t(AX), AX\n"); }
else { emitline("\tMOVZWQ\t(AX), AX\n"); };
}
else { if (esz == 4) {
if (signed_elem) { emitline("\tMOVSXD\t(AX), AX\n"); }
else { emitline("\tMOVL\t(AX), AX\n"); };
}
else { emitline("\tMOVQ\t(AX), AX\n"); };};
else { emitline("\tMOVQ\t(AX), AX\n"); };};};
return;
};
@@ -724,9 +753,19 @@ fn cgslice(c: *cgen, n: *node) void = {
let lo: *node = n.rhs;
let hi: *node = n.cond;
let baselocal: *local = nil;
let globaltn: *node = nil;
let globalname: str;
globalname.ptr = nil; globalname.len = 0;
if (base != nil) {
if (base.kind == nkind.N_IDENT) {
baselocal = localfindnode(c, base.str);
if (baselocal == nil) {
let gt: *node = letvartnode(c, base.str);
if (gt != nil) {
globaltn = gt;
globalname = base.str;
};
};
};
};
// base address
@@ -745,9 +784,22 @@ fn cgslice(c: *cgen, n: *node) void = {
emitoff(baselocal.off: i64);
emitline("(BP), AX\n");
};
} else { if (globaltn != nil) {
// Top-level let: [N]T → LEAQ name(SB); pointer/slice/str
// → MOVQ name(SB) (the symbol holds the {ptr,len,cap} or
// {ptr,len} or pointer value).
if (globaltn.kind == nkind.N_TARRAY) {
emitline("\tLEAQ\t");
emitsymname(c, globalname);
emitline("(SB), AX\n");
} else {
emitline("\tMOVQ\t");
emitsymname(c, globalname);
emitline("(SB), AX\n");
};
} else { if (base != nil) {
cgexpr(c, base);
};};
};};};
emitline("\tPUSHQ\tAX\n");
// lo (default 0)
if (lo != nil) { cgexpr(c, lo); }
@@ -785,9 +837,29 @@ fn cgslice(c: *cgen, n: *node) void = {
};};};
};
if (!handled) { emitline("\tMOVQ\t$0, AX\n"); };
} else { if (globaltn != nil) {
let handled: bool = false;
if (globaltn.kind == nkind.N_TARRAY) {
let lenn: *node = globaltn.rhs;
if (lenn != nil) {
if (lenn.kind == nkind.N_INTLIT) {
emitline("\tMOVQ\t$");
emituint(lenn.uval);
emitline(", AX\n");
handled = true;
};
};
} else { if (globaltn.kind == nkind.N_TSLICE) {
emitline("\tLEAQ\t");
emitsymname(c, globalname);
emitline("(SB), CX\n");
emitline("\tMOVQ\t8(CX), AX\n");
handled = true;
};};
if (!handled) { emitline("\tMOVQ\t$0, AX\n"); };
} else {
emitline("\tMOVQ\t$0, AX\n");
};};
};};};
emitline("\tMOVQ\tAX, BX\n");
emitline("\tPOPQ\tCX\n");
emitline("\tPOPQ\tAX\n");
@@ -1745,7 +1817,21 @@ fn cgun(c: *cgen, n: *node) void = {
};
cgexpr(c, n.lhs);
if (n.op == tkind.TK_MINUS) { emitline("\tNEGQ\tAX\n"); return; };
if (n.op == tkind.TK_TILDE) { emitline("\tNOTQ\tAX\n"); return; };
if (n.op == tkind.TK_TILDE) {
emitline("\tNOTQ\tAX\n");
// NOTQ inverts the whole 64-bit register; clamp narrow
// unsigned results to type width so subsequent 64-bit
// compares against typed literals agree. u32 uses MOVL r,r
// (zero-extends upper 32) because ANDQ $0xFFFFFFFF would
// sign-extend imm32 to all-ones and act as a no-op.
if (nodeisunsigned(c, n.lhs)) {
let w: i32 = nodeprimwidth(c, n.lhs);
if (w == 1) { emitline("\tANDQ\t$255, AX\n"); };
if (w == 2) { emitline("\tANDQ\t$65535, AX\n"); };
if (w == 4) { emitline("\tMOVL\tAX, AX\n"); };
};
return;
};
if (n.op == tkind.TK_STAR) { emitline("\tMOVQ\t(AX), AX\n"); return; };
if (n.op == tkind.TK_NOT) {
let t: str = mklabel(c, "tt");
@@ -2812,8 +2898,9 @@ fn cgassign(c: *cgen, n: *node) void = {
return;
};
if (esz == 1) { emitline("\tMOVB\tAX, (BX)\n"); }
else { if (esz == 2) { emitline("\tMOVW\tAX, (BX)\n"); }
else { if (esz == 4) { emitline("\tMOVL\tAX, (BX)\n"); }
else { emitline("\tMOVQ\tAX, (BX)\n"); };};
else { emitline("\tMOVQ\tAX, (BX)\n"); };};};
return;
};
};