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w6c+w6a+selfhost+lib: cgen+asm bugs surfaced by hash modules

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Seven fixes across the toolchain, plus three new lib/hash modules
(adler32, crc16, crc32) that surfaced them.

  1. `~x` on u8/u16/u32 left the upper bits set: NOTQ inverts the
     whole 64-bit register and nothing trimmed it back to type
     width, so a returned `u16` would compare 64-bit against a
     typed literal and disagree. Both stages now mask after NOTQ
     for narrow unsigned: AND $0xFF/0xFFFF for u8/u16, MOVL r,r for
     u32 (ANDQ $0xFFFFFFFF sign-extends imm32 and is a no-op).
     Signed narrows stay sign-extended and need no fix-up. See
     cmd/w6c/cgen.c N_UN TK_TILDE and selfhost cgenexpr.ww cgun
     TK_TILDE with new nodeprimwidth helper.

  2. w6a had no D_CONST immediate path for ANDQ / ORQ. cgen would
     emit `ANDQ $65535, AX` and the rr encoder silently wrote
     `21 /r` with garbage reg fields — the mask never happened.
     Added `81 /4` (AND) and `81 /1` (OR) imm32 paths in both
     cstage and selfhost w6a. The ~width fix above depends on this.

  3. `s: []u8` cast as a direct fn argument produced a 0-length
     slice. cgexpr for N_CAST left (AX=ptr, BX=len) from the str
     source but never set CX (cap), and the arg-push fallback only
     pushed AX. cgcast now synthesises CX=BX when target is slice
     and source is str; node_isslice / arg-push recognise
     cast-to-slice and emit the full (cap, len, ptr) triple. Both
     stages.

  4. `*[N]T` element-store used 8-byte stride + MOVQ regardless of
     T's width. Indexing `buf: *[4]u16` would step 8 bytes and
     write 8 bytes per element. Added idx_eff (drills *[N]T → T)
     in cstage and the matching pointer-array drill in selfhost
     elemsizeof. Also added MOVW / MOVZWQ / MOVSWQ to w6c, w6a,
     and selfhost mirrors so 2-byte element stores/loads use the
     right opcode (was falling through to MOVQ and trailing 6 bytes
     into the next slot).

  5. Slicing a top-level fixed array (`g[0:n]` where `g: [N]T` is
     a global) computed the base from BP instead of the symbol —
     localfind returned 0 and the cgen treated it as a local at
     offset 0. Both N_SLICE-as-expression (cgslice) and N_SLICE-
     as-call-arg paths now check let_islet / letvartnode and emit
     LEAQ name(SB) when the base is a global array (or MOVQ
     name(SB) for a global slice/pointer base). Both stages.

  6. Top-level `let arr: [N]T = [v0, v1, ...]` link-failed on
     cstage — emit_lets bailed when it saw N_ARRLIT init on an
     array type, and the sz==8 scalar path then misemitted any
     8-byte-sized array (e.g. [4]u16, [8]u8) as a single quad.
     emit_lets now walks N_ARRLIT, evaluates each element as an
     int/rune/bool/nil literal, packs per-element bytes
     little-endian, and honours the trailing `...` repeat marker.
     Selfhost already handled the literal-init path; fixed the
     parallel sz==8 duplicate-DATAW emit on its side (the array
     and the scalar paths both fired, last write winning at link
     but the duplicate broke cross-stage byte-identicality on user
     code with this shape).

  7. w6a's per-line input buffer was a 1KB stack `char buf[1024]`.
     A `DATAW` for a [256]u16 emits ~2080 bytes on one line, which
     truncated mid-escape; the assembler then re-parsed the
     remaining tail as garbage opcodes ("unknown opcode"). Bumped
     cstage w6a to a 32K static buffer (selfhost w6a already
     allocated per-line via amalloc).

  lib: lib/hash/adler32, lib/hash/crc16, lib/hash/crc32 — pure
  buffer-subset shape (matching lib/hash/fnv), with per-module
  *_test.ww runnable via `ww test lib/hash/<name>`. Adler-32 plus
  CRC-16 (CCITT/CMDA2000/DECT/ANSI) and CRC-32 (IEEE/Castagnoli/
  Koopman) cover Hare's reference vectors bit-for-bit. Wired into
  test/wcc/900_stdlib.c. .gitignore: lib/**/*.s,*.o so `ww test`
  droppings stay untracked.

`make test` (26/26), `make bootstrap` (ww2≡ww3≡ww4), and per-module
`ww test` all pass. cgen output is byte-identical across cstage and
selfhost for every repro that previously diverged.
This commit is contained in:
Hojun-Cho
2026-05-13 14:26:18 +09:00
parent b05968c7f4
commit cbcc0167ae
22 changed files with 1242 additions and 59 deletions
Download Patch File Download Diff File Expand all files Collapse all files

82
selfhost/cmd/w6a/asm.ww
View File

@@ -443,6 +443,62 @@ export fn encode(a: *asm_) i32 = {
p = p.link; continue;
};
if (op == A_MOVW) {
// 16-bit MOV: 0x66 operand-size prefix + the 32-bit
// MOV opcodes 0x89 / 0x8B. No REX.W.
let ft: i32 = p.from.atype;
let tt: i32 = p.to.atype;
if (isgpr(ft)) { if (tt == D_INDIR) {
emitbyte(a, 102u8); // 0x66
emitrex(a, rhi(ft), rhi(p.to.reg), 0);
emitbyte(a, 137u8); // 0x89
emitmodrmmem(a, rcode(ft), p.to.reg, p.to.offset);
p = p.link; continue;
};};
if (ft == D_INDIR) { if (isgpr(tt)) {
emitbyte(a, 102u8); // 0x66
emitrex(a, rhi(tt), rhi(p.from.reg), 0);
emitbyte(a, 139u8); // 0x8B
emitmodrmmem(a, rcode(tt), p.from.reg, p.from.offset);
p = p.link; continue;
};};
os.write(2, "w6a: unsupported MOVW shape\n".ptr, 27u64);
a.errs += 1;
p = p.link; continue;
};
if (op == A_MOVZWQ) {
// MOVZX r64, r/m16 — 0F B7 /r with REX.W.
let ft: i32 = p.from.atype;
let tt: i32 = p.to.atype;
if (ft == D_INDIR) { if (isgpr(tt)) {
emitrex(a, rhi(tt), rhi(p.from.reg), 1);
emitbyte(a, 15u8);
emitbyte(a, 183u8); // 0xB7
emitmodrmmem(a, rcode(tt), p.from.reg, p.from.offset);
p = p.link; continue;
};};
os.write(2, "w6a: unsupported MOVZWQ shape\n".ptr, 29u64);
a.errs += 1;
p = p.link; continue;
};
if (op == A_MOVSWQ) {
// MOVSX r64, r/m16 — 0F BF /r with REX.W.
let ft: i32 = p.from.atype;
let tt: i32 = p.to.atype;
if (ft == D_INDIR) { if (isgpr(tt)) {
emitrex(a, rhi(tt), rhi(p.from.reg), 1);
emitbyte(a, 15u8);
emitbyte(a, 191u8); // 0xBF
emitmodrmmem(a, rcode(tt), p.from.reg, p.from.offset);
p = p.link; continue;
};};
os.write(2, "w6a: unsupported MOVSWQ shape\n".ptr, 29u64);
a.errs += 1;
p = p.link; continue;
};
if (op == A_MOVZBQ) {
let ft: i32 = p.from.atype;
let tt: i32 = p.to.atype;
@@ -607,8 +663,30 @@ export fn encode(a: *asm_) i32 = {
p = p.link; continue;
};
if (op == A_ANDQ) { encoderr(a, 33u8, p.from.atype, p.to.atype); p = p.link; continue; }; // 0x21
if (op == A_ORQ) { encoderr(a, 9u8, p.from.atype, p.to.atype); p = p.link; continue; }; // 0x09
if (op == A_ANDQ) {
// AND r/m64, imm32 — 0x81 /4 (REX.W). Without the
// D_CONST path encoderr would silently emit 0x21
// with garbage reg fields.
let ft: i32 = p.from.atype;
let tt: i32 = p.to.atype;
if (ft == D_CONST) { if (isgpr(tt)) {
encoderiimm32(a, 129u8, 4, tt, p.from.offset: i32);
p = p.link; continue;
};};
encoderr(a, 33u8, ft, tt); // 0x21
p = p.link; continue;
};
if (op == A_ORQ) {
// OR r/m64, imm32 — 0x81 /1 (REX.W). Mirrors ANDQ.
let ft: i32 = p.from.atype;
let tt: i32 = p.to.atype;
if (ft == D_CONST) { if (isgpr(tt)) {
encoderiimm32(a, 129u8, 1, tt, p.from.offset: i32);
p = p.link; continue;
};};
encoderr(a, 9u8, ft, tt); // 0x09
p = p.link; continue;
};
if (op == A_XORQ) {
let ft: i32 = p.from.atype;
let tt: i32 = p.to.atype;