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cgen: f64-typed int-literal + tuple-field materialize in X0 (both stages, #103)

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Two sites, same class: an f64 value failing to reach XMM (X0) before an
SSE op. Both gate-blind — cstage and wwstage emitted the same wrong asm —
so the fix touches both stages identically.

FACE X — a no-decimal float-typed integer literal (`0f64`, `8f64`) is an
N_INTLIT carrying float TYPE. The integer-immediate path stranded it in
AX, so `n == 0f64` compared a stale X0 (true for all n) and
`(8f64 * 10.0): i32` read garbage. Route the float-typed N_INTLIT through
the float-constant-in-X0 emit (cgen.c cgexpr_float, factored from
N_FLOATLIT; cgenexpr.ww cgfloatbits). The wwstage also needs the
exprfloatkind N_INTLIT arm so the downstream f64->i32 cast emits
CVTTSD2SI not MOVSXD — cstage reads the checker-stamped type directly,
so this is the same #101 structural-vs-stamped asymmetry.

FACE Z — a tuple positional f64 field read (`r.0`, r:(f64,i64)) loaded
via the integer op into AX, so `r.0 == 0.0` was wrongly true. Add a
fld_isfloat branch -> MOVSD/MOVSS into X0 (cgen.c:5910 tuple arm;
cgenexpr.ww tuple arm), mirroring the struct-field float load at
cgen.c:1462,1838 (the #96 pattern).
This commit is contained in:
Hojun-Cho
2026-05-25 15:26:43 +09:00
parent e784968dd8
commit c9e39c6782
3 changed files with 92 additions and 21 deletions
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59
selfhost/cmd/wcc/cgenexpr.ww
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@@ -21,11 +21,37 @@ import typ;
import sym;
import strconv;
// cgfloatbits — materialise a float constant in X0: MOVQ the IEEE bits
// into AX, PUSH, MOVSD off the stack into X0. Shared by N_FLOATLIT (bits
// already in n.uval from the lexer's bitcast) and the f64/f32-typed
// N_INTLIT arm (#103 FACE X).
fn cgfloatbits(c: *cgen, bits: u64) void = {
emitline("\tMOVQ\t$");
emitint(bits: i64);
emitline(", AX\n");
emitline("\tPUSHQ\tAX\n");
emitline("\tMOVSD\t(SP), X0\n");
emitline("\tADDQ\t$8, SP\n");
};
fn cgexpr(c: *cgen, n: *node) void = {
if (n == nil) { return; };
let k: nkind = n.kind;
if (k == nkind.N_INTLIT) {
// A no-decimal `0f64`/`8f64` is an N_INTLIT carrying float
// TYPE; it must reach X0 like a true float literal, not the
// integer-immediate path (which strands it in AX and an SSE
// compare/mul reads a stale X0 — #103 FACE X). The bits are
// the IEEE pattern of the integer value, mirroring cstage's
// `(double)(long long)n->uval`; the (&fv):*u64 bitcast is the
// lex.ww idiom (lib/ww/lex/lex.ww).
if (isfloattype(c, n)) {
let fv: f64 = (n.uval: i64): f64;
let pu: *u64 = (&fv): *u64;
cgfloatbits(c, *pu);
return;
};
// Print signed (i64), not unsigned (u64). C cgen uses
// `$%lld` so 64-bit constants with bit 63 set show up as
// negative — e.g. FNV-1a's offset basis prints as
@@ -36,19 +62,11 @@ fn cgexpr(c: *cgen, n: *node) void = {
return;
};
if (k == nkind.N_FLOATLIT) {
// Materialise the f64 bit pattern in AX, push, then MOVSD it
// into X0. The bits come from n.uval — the parser populates
// it from the lexer's bitcast of t.fval, so this path stays
// integer-only (no SSE in the cgen source). The f32
// narrowing is handled at the consumer site, not here — the
// literal always carries the full double precision until
// typed by context.
emitline("\tMOVQ\t$");
emitint(n.uval: i64);
emitline(", AX\n");
emitline("\tPUSHQ\tAX\n");
emitline("\tMOVSD\t(SP), X0\n");
emitline("\tADDQ\t$8, SP\n");
// The bits come from n.uval — the parser populates it from
// the lexer's bitcast of t.fval. The f32 narrowing is handled
// at the consumer site, not here — the literal always carries
// the full double precision until typed by context.
cgfloatbits(c, n.uval);
return;
};
if (k == nkind.N_RUNELIT) {
@@ -1652,6 +1670,21 @@ fn cgdot(c: *cgen, n: *node) void = {
emitline("(BP), CX\n");
return;
};
// f64/f32 tuple field must ride X0 via
// MOVSD/MOVSS; the integer load op left it
// in AX (#103 FACE Z). Mirrors the float
// local load above and cstage cgen.c:1462,
// 1838 (the #96 pattern).
if (isfloattype(c, tpt)) {
let mov: str = "MOVSD";
if (isf32type(c, tpt)) { mov = "MOVSS"; };
emitline("\t");
emitline(mov);
emitline("\t");
emitoff((lc.off + foff): i64);
emitline("(BP), X0\n");
return;
};
let sz: i32 = slotsize(c, tpt);
let op: str = tnodeloadop(c, tpt, sz);
emitline("\t");