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selfhost: drop snake_case locals in dyn/dynout/obj + w6a + cgen + ww driver

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Hojun-Cho
2026-05-11 16:33:02 +09:00
parent c64e96cbd6
commit 97ca76d2bb
18 changed files with 1795 additions and 1795 deletions
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46
selfhost/cmd/w6a/asm.ww
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@@ -99,21 +99,21 @@ fn emitrex(a: *asm_, regbit: i32, rmbit: i32, w: i32) void = {
// ModR/M + (optional) SIB + displacement for [base+disp].
// Special-cases SP (needs SIB) and BP (forces explicit disp).
fn emitmodrmmem(a: *asm_, reg_field: i32, base: i32, disp: i64) void = {
fn emitmodrmmem(a: *asm_, regfield: i32, base: i32, disp: i64) void = {
let rm: i32 = rcode(base);
let needsib: bool = (rm == 4);
let forced_disp: bool = false;
if (rm == 5) { if (disp == 0i64) { forced_disp = true; }; };
let forceddisp: bool = false;
if (rm == 5) { if (disp == 0i64) { forceddisp = true; }; };
let mod: i32 = 2;
if (disp == 0i64) {
if (!forced_disp) { mod = 0; }
if (!forceddisp) { mod = 0; }
else { mod = 1; };
} else {
if (disp >= -128i64) { if (disp <= 127i64) { mod = 1; }; };
};
emitbyte(a, modrmbyte(mod, reg_field, rm));
emitbyte(a, modrmbyte(mod, regfield, rm));
if (needsib) {
emitbyte(a, 36u8); // 0x24: scale=0 idx=4(none) base=4
};
@@ -132,17 +132,17 @@ fn encoderr(a: *asm_, opcode: u8, src: i32, dst: i32) void = {
};
// reg→mem(base, disp) (e.g. MOVQ src reg into mem; opcode = 0x89).
fn encoderm(a: *asm_, opcode: u8, src_reg: i32, base: i32, disp: i64) void = {
emitrex(a, rhi(src_reg), rhi(base), 1);
fn encoderm(a: *asm_, opcode: u8, srcreg: i32, base: i32, disp: i64) void = {
emitrex(a, rhi(srcreg), rhi(base), 1);
emitbyte(a, opcode);
emitmodrmmem(a, rcode(src_reg), base, disp);
emitmodrmmem(a, rcode(srcreg), base, disp);
};
// mem(base, disp) → reg (e.g. MOVQ mem into reg; opcode = 0x8B).
fn encodemr(a: *asm_, opcode: u8, dst_reg: i32, base: i32, disp: i64) void = {
emitrex(a, rhi(dst_reg), rhi(base), 1);
fn encodemr(a: *asm_, opcode: u8, dstreg: i32, base: i32, disp: i64) void = {
emitrex(a, rhi(dstreg), rhi(base), 1);
emitbyte(a, opcode);
emitmodrmmem(a, rcode(dst_reg), base, disp);
emitmodrmmem(a, rcode(dstreg), base, disp);
};
// OPCODE /n imm32 reg form (e.g. ADDQ $imm, reg).
@@ -162,29 +162,29 @@ fn encodeunary(a: *asm_, opcode: u8, subop: i32, dst: i32) void = {
// SSE2 helpers. Plan 9 syntax: source first, destination second.
// For ADDSD-style ops we put dst in the reg field, src in r/m.
fn sserr(a: *asm_, prefix: u8, op2: u8, reg_op: i32, rm_op: i32) void = {
fn sserr(a: *asm_, prefix: u8, op2: u8, regop: i32, rmop: i32) void = {
if (prefix != 0u8) { emitbyte(a, prefix); };
emitrex(a, rhi(reg_op), rhi(rm_op), 0);
emitrex(a, rhi(regop), rhi(rmop), 0);
emitbyte(a, 15u8); // 0x0F
emitbyte(a, op2);
emitbyte(a, modrmbyte(3, rcode(reg_op), rcode(rm_op)));
emitbyte(a, modrmbyte(3, rcode(regop), rcode(rmop)));
};
fn ssemrload(a: *asm_, prefix: u8, op2: u8, reg_op: i32, base: i32, disp: i64) void = {
fn ssemrload(a: *asm_, prefix: u8, op2: u8, regop: i32, base: i32, disp: i64) void = {
if (prefix != 0u8) { emitbyte(a, prefix); };
emitrex(a, rhi(reg_op), rhi(base), 0);
emitrex(a, rhi(regop), rhi(base), 0);
emitbyte(a, 15u8);
emitbyte(a, op2);
emitmodrmmem(a, rcode(reg_op), base, disp);
emitmodrmmem(a, rcode(regop), base, disp);
};
// REX.W variant of sse_rr (CVTTSD2SI / CVTSI2SD).
fn sserrw(a: *asm_, prefix: u8, op2: u8, reg_op: i32, rm_op: i32) void = {
fn sserrw(a: *asm_, prefix: u8, op2: u8, regop: i32, rmop: i32) void = {
if (prefix != 0u8) { emitbyte(a, prefix); };
emitrex(a, rhi(reg_op), rhi(rm_op), 1);
emitrex(a, rhi(regop), rhi(rmop), 1);
emitbyte(a, 15u8);
emitbyte(a, op2);
emitbyte(a, modrmbyte(3, rcode(reg_op), rcode(rm_op)));
emitbyte(a, modrmbyte(3, rcode(regop), rcode(rmop)));
};
// ---- label resolution / fixups ----------------------------------------
@@ -629,7 +629,7 @@ export fn encode(a: *asm_) i32 = {
// Conditional jumps. 0x0F + cc + rel32.
let cc: u8 = 0u8;
let is_jcc: bool = true;
let isjcc: bool = true;
if (op == A_JE) { cc = 132u8; } // 0x84
else { if (op == A_JZ) { cc = 132u8; }
else { if (op == A_JNE) { cc = 133u8; }
@@ -642,8 +642,8 @@ export fn encode(a: *asm_) i32 = {
else { if (op == A_JBE) { cc = 134u8; }
else { if (op == A_JA) { cc = 135u8; }
else { if (op == A_JAE) { cc = 131u8; }
else { is_jcc = false; };};};};};};};};};};};};
if (is_jcc) {
else { isjcc = false; };};};};};};};};};};};};
if (isjcc) {
emitbyte(a, 15u8);
emitbyte(a, cc);
addfixup(a, a.textlen, p.to.asym);