cstage+selfhost+test: f64 variant-widen via MOVSD from X0 (#30)
Initializing a tagged-union variant slot with a runtime f64 source (let, cast, fn call, unary, struct field, etc.) stored the i64 bit pattern in the payload, not the float bit pattern. cgexpr leaves f64 in X0; the existing scalar-fallback MOVQ-from-AX wrote whatever was last in AX (typically pre-conversion integer or stale residue). Worker-fmtfloat surfaced this during #17 pre-flight (probe at .ai/probe_f64_union_widen.ww). Blocks #17 fmt.float dispatch arm. TK_FLOAT literals were coincidentally correct because the lowering loads bits into AX before passing through X0 — the literal_1_0 test row pins that as the principled MOVSD path now. cstage cg_widen_tagged_store: add fld_isfloat arm between the slice and scalar fallbacks. Emit MOVSD (f64) / MOVSS (f32) from X0 to the payload offset, then the tag MOVQ. Mirrors existing str/slice/ structlit field-flow dispatchers. Wwstage cgwidentaggedstorebp: mirror via exprfloatkind. Resolves a secondary gap by looking up the variant tag directly via flatvariantidx(c, dt, "f64"/"f32") — rhstargetname has no N_FLOATLIT / N_CALL / N_DOT branch and would fall through to str-fallback returning tag 0. No in-tree consumer triggered this pre-fix (no f64 in any tagged union yet) — hence latent silence. arr[i]= and append() have the same class gap but no in-tree exerciser today; same shape if/when [N]f64 / []f64 land. Test 715 (tagged_widen_f64): 7 rows × 2 stages = 14 fixtures with bit-pinning via *u8 punning. literal_1_0 (regression lock-in), cast_1_f64, call_makeone, unary_neg_f64, ident_f64, field_f64 (rob's extra row), i64_rhs_still_integer (negative control). Diagnosable 0/1/2 return codes distinguish pass / wrong-tag / wrong-payload. ww2 == ww3 == ww4 byte-identical post-fix.
This commit is contained in:
7
Makefile
7
Makefile
@@ -238,6 +238,7 @@ TESTS = $(BIN)/test_smoke $(BIN)/test_lex $(BIN)/test_parse $(BIN)/test_check \
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$(BIN)/test_redecl \
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$(BIN)/test_struct_field_index \
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$(BIN)/test_tagged_return_scratch \
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$(BIN)/test_tagged_widen_f64 \
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$(BIN)/test_param_shadow_mod \
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$(BIN)/test_localoff_scope \
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$(BIN)/test_cast_enum_movl \
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@@ -477,6 +478,12 @@ $(BIN)/test_tagged_return_scratch: test/wcc/714_tagged_return_scratch.c \
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$(LIB)/libwwrt.a | $(BIN)
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$(CC) $(CFLAGS) -o $@ $<
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$(BIN)/test_tagged_widen_f64: test/wcc/715_tagged_widen_f64.c \
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$(BIN)/ww $(BIN)/w6c $(BIN)/w6a $(BIN)/w6l \
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$(BIN)/ww_ww $(BIN)/w6c_ww $(BIN)/w6a_ww $(BIN)/w6l_ww \
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$(LIB)/libwwrt.a | $(BIN)
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$(CC) $(CFLAGS) -o $@ $<
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$(BIN)/test_use_promote_alias: test/wcc/699_use_promote_alias.c \
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$(BIN)/ww $(BIN)/w6c $(BIN)/w6a $(BIN)/w6l \
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$(LIB)/libwwrt.a | $(BIN)
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@@ -1295,6 +1295,25 @@ cg_widen_tagged_store(Cg *c, Local **locals_p, Type *dst, Node *src,
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if (via_outer) goto copy_out;
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return;
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}
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/* Float arm: cgexpr on an f64/f32 source leaves the bit pattern in
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* X0 only — the AX-store below would silently write whatever was
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* loaded into AX before the SSE conversion. Literal `1.0` works by
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* coincidence (TK_FLOAT lowering loads the f64 bit pattern into AX
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* before MOVSD'ing into X0); every runtime f64 shape (cast, call,
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* unary, ident, struct-field load) needs the explicit MOVSD path.
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* Same kind-specific dispatch as the str/slice branches above and
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* the structlit field-flow at the top of this function. */
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int wid_isf32 = 0;
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if (fld_isfloat(st, &wid_isf32)) {
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int mov = wid_isf32 ? A_MOVSS : A_MOVSD;
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cgexpr(c, src, *locals_p);
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ins2(c, mov, areg(D_X0), amem(D_BP, write_off + 8));
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int tag = cg_tag_for_variant(du, st);
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ins2(c, A_MOVQ, aimm(tag < 0 ? 0 : tag),
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amem(D_BP, write_off + 0));
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if (via_outer) goto copy_out;
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return;
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}
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/* Scalar / pointer / etc. The high slot word (when sz > 16) is
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* left untouched here — match dispatches on the tag word first
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* and only the str branch reads slot+16, so leaving the pad
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@@ -9110,6 +9110,37 @@ fn cgwidentaggedstorebp(c: *cgen, dst: *node, src: *node, slot_off: i32, slot_sz
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emitline("(BP)\n");
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return;
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};
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// Float arm: cgexpr on an f64/f32 source leaves the bit pattern in
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// X0 only — the AX-store fallback below would silently write whatever
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// was loaded into AX before the SSE conversion. Literal `1.0` works
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// by coincidence (TK_FLOAT lowering loads the f64 bit pattern into AX
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// before MOVSD'ing into X0); every runtime f64 shape (cast, call,
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// unary, ident, struct-field load) needs the explicit MOVSD path.
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// Mirror of cstage cg_widen_tagged_store's float arm. Wwstage has no
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// checker so we classify via exprfloatkind (same shape used by cgcast)
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// and resolve the variant tag by name directly — rhstargetname has no
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// N_FLOATLIT / N_CALL / N_DOT branch and would fall through to the
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// str-shape fallback that picks tag 0 for an `(i64 | f64)` union.
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let fkind: i32 = exprfloatkind(c, src);
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if (fkind != 0) {
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let fmov: str = "MOVSD";
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let fname: str = "f64";
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if (fkind == 1) { fmov = "MOVSS"; fname = "f32"; };
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cgexpr(c, src);
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emitline("\t");
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emitline(fmov);
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emitline("\tX0, ");
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emitoff((slot_off + 8): i64);
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emitline("(BP)\n");
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let ftag: i32 = flatvariantidx(c, dt, fname);
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if (ftag < 0) { ftag = 0; };
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emitline("\tMOVQ\t$");
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emitint(ftag: i64);
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emitline(", ");
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emitoff(slot_off: i64);
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emitline("(BP)\n");
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return;
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};
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// Scalar payload.
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cgexpr(c, src);
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emitline("\tMOVQ\tAX, ");
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@@ -2867,6 +2867,37 @@ fn cgwidentaggedstorebp(c: *cgen, dst: *node, src: *node, slot_off: i32, slot_sz
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emitline("(BP)\n");
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return;
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};
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// Float arm: cgexpr on an f64/f32 source leaves the bit pattern in
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// X0 only — the AX-store fallback below would silently write whatever
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// was loaded into AX before the SSE conversion. Literal `1.0` works
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// by coincidence (TK_FLOAT lowering loads the f64 bit pattern into AX
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// before MOVSD'ing into X0); every runtime f64 shape (cast, call,
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// unary, ident, struct-field load) needs the explicit MOVSD path.
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// Mirror of cstage cg_widen_tagged_store's float arm. Wwstage has no
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// checker so we classify via exprfloatkind (same shape used by cgcast)
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// and resolve the variant tag by name directly — rhstargetname has no
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// N_FLOATLIT / N_CALL / N_DOT branch and would fall through to the
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// str-shape fallback that picks tag 0 for an `(i64 | f64)` union.
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let fkind: i32 = exprfloatkind(c, src);
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if (fkind != 0) {
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let fmov: str = "MOVSD";
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let fname: str = "f64";
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if (fkind == 1) { fmov = "MOVSS"; fname = "f32"; };
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cgexpr(c, src);
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emitline("\t");
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emitline(fmov);
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emitline("\tX0, ");
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emitoff((slot_off + 8): i64);
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emitline("(BP)\n");
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let ftag: i32 = flatvariantidx(c, dt, fname);
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if (ftag < 0) { ftag = 0; };
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emitline("\tMOVQ\t$");
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emitint(ftag: i64);
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emitline(", ");
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emitoff(slot_off: i64);
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emitline("(BP)\n");
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return;
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};
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// Scalar payload.
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cgexpr(c, src);
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emitline("\tMOVQ\tAX, ");
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@@ -9110,6 +9110,37 @@ fn cgwidentaggedstorebp(c: *cgen, dst: *node, src: *node, slot_off: i32, slot_sz
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emitline("(BP)\n");
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return;
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};
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// Float arm: cgexpr on an f64/f32 source leaves the bit pattern in
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// X0 only — the AX-store fallback below would silently write whatever
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// was loaded into AX before the SSE conversion. Literal `1.0` works
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// by coincidence (TK_FLOAT lowering loads the f64 bit pattern into AX
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// before MOVSD'ing into X0); every runtime f64 shape (cast, call,
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// unary, ident, struct-field load) needs the explicit MOVSD path.
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// Mirror of cstage cg_widen_tagged_store's float arm. Wwstage has no
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// checker so we classify via exprfloatkind (same shape used by cgcast)
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// and resolve the variant tag by name directly — rhstargetname has no
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// N_FLOATLIT / N_CALL / N_DOT branch and would fall through to the
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// str-shape fallback that picks tag 0 for an `(i64 | f64)` union.
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let fkind: i32 = exprfloatkind(c, src);
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if (fkind != 0) {
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let fmov: str = "MOVSD";
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let fname: str = "f64";
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if (fkind == 1) { fmov = "MOVSS"; fname = "f32"; };
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cgexpr(c, src);
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emitline("\t");
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emitline(fmov);
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emitline("\tX0, ");
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emitoff((slot_off + 8): i64);
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emitline("(BP)\n");
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let ftag: i32 = flatvariantidx(c, dt, fname);
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if (ftag < 0) { ftag = 0; };
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emitline("\tMOVQ\t$");
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emitint(ftag: i64);
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emitline(", ");
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emitoff(slot_off: i64);
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emitline("(BP)\n");
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return;
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};
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// Scalar payload.
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cgexpr(c, src);
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emitline("\tMOVQ\tAX, ");
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237
test/wcc/715_tagged_widen_f64.c
Normal file
237
test/wcc/715_tagged_widen_f64.c
Normal file
@@ -0,0 +1,237 @@
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/*
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* 715_tagged_widen_f64 — variant-widen into a tagged-union slot must
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* route f64/f32 sources through the SSE register (X0) instead of the
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* integer AX. Pre-fix cg_widen_tagged_store / cgwidentaggedstorebp fell
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* through to a single "scalar payload" arm that always emitted
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* `MOVQ AX, slot+8(BP)`; for an f64 source cgexpr leaves the bit pattern
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* in X0 only and AX holds the pre-conversion integer (or any prior
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* temp). The literal-f64 case worked by coincidence because TK_FLOAT
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* lowering happens to load the f64 bit pattern into AX before the
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* MOVSD into X0; every runtime-f64 shape (cast, call, unary, ident,
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* struct-field load) silently miscompiled.
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*
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* Surfaced by worker-fmtfloat probe during the #17 (fmt float dispatch
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* arm) pre-flight. Closed by adding an `fld_isfloat(st, ...)` /
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* `exprfloatkind(c, src)` arm ahead of the scalar fallback in both
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* stages — same kind-specific dispatch as the existing str / slice
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* branches and the structlit-field-flow MOVSD arm.
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*
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* Coverage is bit-level: each row punts the tagged-union slot through
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* `*u8` and reads payload bits as u64, so a tag-only or low-32-bits-only
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* store fails the row instead of silently approximating. The expected
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* payload for f64 1.0 is 0x3FF0000000000000 == 4607182418800017408.
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*
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* Rows:
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* literal_1_0 — `1.0` typed by surface form. Pre-fix passed
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* by coincidence (MOVQ AX path happened to
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* hold the right bits); pin it explicitly so
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* a future cgexpr refactor that changes the
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* constant-load shape can't silently regress.
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* cast_1_f64 — `1: f64`. Cast-peel keeps the cast (dest is
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* a concrete variant, not the union), so the
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* CVTSI2SD's X0 result must flow through
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* MOVSD.
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* call_makeone — fn returning f64. X0-ABI return.
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* unary_neg_f64 — `-(1: f64)`. N_UN(MINUS, N_CAST) over f64;
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* cgun keeps the value in X0.
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* ident_f64 — concrete f64 local. cgexpr emits a MOVSD
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* load to X0; AX is untouched.
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* field_f64 — load from a struct field of type f64.
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* Exercises the field-read shape through
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* cgexpr; same X0-only ABI.
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*
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* One extra row pins the negative case: an i64 rhs of the same union
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* must still emit MOVQ AX (the float arm is gated on the source's
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* float-class, not on the dst variant set).
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*
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* Note: this is a regression cover for the same path that blocks #17
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* (fmt float dispatch arm). No in-tree caller exercised the path
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* pre-fix, hence the latent silence; #17 will be the first consumer.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include <sys/stat.h>
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#include <sys/wait.h>
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static int
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runwait(const char *cmd)
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{
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int rc = system(cmd);
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if (rc == -1) return -1;
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if (WIFEXITED(rc)) return WEXITSTATUS(rc);
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return -1;
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}
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struct row { const char *label; const char *src; int want; };
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/* Bit-pin via `*u8` cast → payload at slot+8, tag at slot+0. Returns
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* 0 if payload bits and tag both match expected
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* 1 if tag wrong
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* 2 if payload bits wrong (the f64 miscompile signature)
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* Driver checks `got == 0`. */
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#define BITCHECK_F64(union_decl, init_stmt, want_bits, want_tag) \
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union_decl \
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"fn main() i32 = {\n" \
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" " init_stmt \
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" let pp: *(i64 | f64) = &a;\n" \
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" let pu: *u8 = pp: *u8;\n" \
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" let tagp: *i64 = pu: *i64;\n" \
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" let payp: *u64 = (pu + 8u64): *u64;\n" \
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" if (*tagp != " want_tag "i64) { return 1; };\n" \
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" if (*payp != " want_bits "u64) { return 2; };\n" \
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" return 0;\n" \
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"};\n"
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static const struct row rows[] = {
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/* Literal 1.0 — already-correct lock-in. TK_FLOAT lowering
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* loaded the f64 bits into AX so MOVQ wrote the right value;
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* after the fix it goes through the principled MOVSD path. */
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{ "literal_1_0",
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BITCHECK_F64(
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"",
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"let a: (i64 | f64) = 1.0;\n",
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"4607182418800017408", "1"),
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0 },
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/* Runtime cast: `1: f64`. Pre-fix wrote integer 1 into payload. */
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{ "cast_1_f64",
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BITCHECK_F64(
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"",
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"let a: (i64 | f64) = 1: f64;\n",
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"4607182418800017408", "1"),
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0 },
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/* Fn returning f64 — X0-ABI return. cgexpr on N_CALL leaves the
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* value in X0, AX holds the return-value index / 0. */
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{ "call_makeone",
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BITCHECK_F64(
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"fn makeone() f64 = { return 1: f64; };\n",
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"let a: (i64 | f64) = makeone();\n",
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"4607182418800017408", "1"),
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0 },
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/* Unary minus over an f64 cast — value stays in X0 through cgun. */
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{ "unary_neg_f64",
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BITCHECK_F64(
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"",
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"let a: (i64 | f64) = -(1: f64);\n",
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/* -1.0 == 0xBFF0000000000000 == 13830554455654793216 */
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"13830554455654793216", "1"),
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0 },
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/* Concrete f64 ident — cgexpr emits MOVSD load to X0; AX is
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* never touched. */
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{ "ident_f64",
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BITCHECK_F64(
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"",
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"let f: f64 = 1: f64;\n"
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" let a: (i64 | f64) = f;\n",
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"4607182418800017408", "1"),
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0 },
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/* Struct-field of type f64 — exercises the field-read shape
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* through cgexpr. Same X0-only ABI as plain idents. */
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{ "field_f64",
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BITCHECK_F64(
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"type holder = struct { v: f64, pad: i32 };\n",
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"let h: holder;\n"
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" h.v = 1: f64;\n"
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" let a: (i64 | f64) = h.v;\n",
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"4607182418800017408", "1"),
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0 },
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/* Negative control: i64 rhs into the same union must still hit
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* the integer arm (MOVQ AX). Pre-fix this also worked; the float
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* arm must not shadow it. Tag = 0 (i64 is variant 0). */
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{ "i64_rhs_still_integer",
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BITCHECK_F64(
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"",
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"let a: (i64 | f64) = 7i64;\n",
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"7", "0"),
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0 },
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};
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static int
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run_driver(const char *driver, const struct row *r, int i)
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{
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char src[64], tmpdir[64], cmd[1024];
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snprintf(src, sizeof src, "/tmp/twf64_%d_%d.ww", getpid(), i);
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snprintf(tmpdir, sizeof tmpdir, "/tmp/twf64_%d_d_%d", getpid(), i);
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FILE *f = fopen(src, "wb");
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if (!f) return -1;
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fputs(r->src, f);
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fclose(f);
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mkdir(tmpdir, 0755);
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snprintf(cmd, sizeof cmd, "cd %s && %s build %s",
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tmpdir, driver, src);
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if (runwait(cmd) != 0) {
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fprintf(stderr, "row[%s]: build via %s failed\n",
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r->label, driver);
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unlink(src); rmdir(tmpdir);
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return -1;
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}
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const char *base = strrchr(src, '/');
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base = base ? base + 1 : src;
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char outbin[128];
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snprintf(outbin, sizeof outbin, "%s/%s", tmpdir, base);
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char *dot = strrchr(outbin, '.');
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if (dot && strcmp(dot, ".ww") == 0) *dot = '\0';
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int got = runwait(outbin);
|
||||
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||||
unlink(src); unlink(outbin); rmdir(tmpdir);
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||||
return got;
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||||
}
|
||||
|
||||
int
|
||||
main(void)
|
||||
{
|
||||
const char *bin = getenv("BIN");
|
||||
if (!bin) bin = "out/bin";
|
||||
char absbin[1024];
|
||||
if (bin[0] != '/') {
|
||||
char cwd[1024];
|
||||
if (getcwd(cwd, sizeof cwd) == NULL) return 1;
|
||||
snprintf(absbin, sizeof absbin, "%s/%s", cwd, bin);
|
||||
bin = absbin;
|
||||
}
|
||||
|
||||
char cdrv[1024];
|
||||
snprintf(cdrv, sizeof cdrv, "%s/ww", bin);
|
||||
char wdrv[1024];
|
||||
snprintf(wdrv, sizeof wdrv, "%s/ww_ww", bin);
|
||||
|
||||
struct { const char *name; const char *path; int gated_on_existence; }
|
||||
drivers[] = {
|
||||
{ "cstage", cdrv, 0 },
|
||||
{ "wwstage", wdrv, 1 },
|
||||
{ NULL, NULL, 0 },
|
||||
};
|
||||
|
||||
int n = (int)(sizeof rows / sizeof rows[0]);
|
||||
int total = 0, fail = 0;
|
||||
for (int d = 0; drivers[d].name; d++) {
|
||||
if (drivers[d].gated_on_existence
|
||||
&& access(drivers[d].path, X_OK) != 0) {
|
||||
fprintf(stderr, "tagged_widen_f64: skip %s (no %s)\n",
|
||||
drivers[d].name, drivers[d].path);
|
||||
continue;
|
||||
}
|
||||
for (int i = 0; i < n; i++) {
|
||||
int got = run_driver(drivers[d].path, &rows[i], i);
|
||||
total++;
|
||||
if (got != rows[i].want) {
|
||||
fprintf(stderr,
|
||||
"tagged_widen_f64[%s][%s]: exit=%d want=%d\n",
|
||||
drivers[d].name, rows[i].label,
|
||||
got, rows[i].want);
|
||||
fail++;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (fail) {
|
||||
fprintf(stderr,
|
||||
"tagged_widen_f64: %d/%d fixtures failed\n", fail, total);
|
||||
return 1;
|
||||
}
|
||||
printf("tagged_widen_f64: %d/%d ok\n", total, total);
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user