w6c+wcc+selfhost+lib: int-cast truncate + use_alias, 5 new modules

Two cgen/check bugs surfaced by new lib modules, plus the modules
themselves (crc64, siphash, random, base64, base32).

  1. `(big_u64): u32` (and `: u16`, `: u8`, `: bool`) didn't truncate.
     N_CAST emitted nothing for int↔int; the value stayed in AX with
     its upper bits intact and downstream CMPQ/DIVQ misread the slot.
     The TK_TILDE path already had clamp logic for the same reason —
     N_CAST was the missing case. Both stages now MOVL r,r for u32 and
     ANDQ $mask for u8/u16/bool. Signed-narrow (i8/i16/i32) stays
     no-op until w6a grows reg-reg MOVSBQ/MOVSWQ/MOVSXD. selfhost
     cgcast walks alias chains via aliaslookup before checking
     primsize/typenameisunsigned so `(u: random)` where
     `type random = u64` still bypasses the clamp.
     See cmd/w6c/cgen.c N_CAST and selfhost/cmd/wcc/cgenexpr.ww cgcast.

  2. `mod.mod` type refs (`random.random` when the imported module
     declares `export type random = u64;`) failed with "unknown type".
     The driver concatenates imports into one flat scope, so SK_USE
     `random` collided with SK_TYPE `random` and scope_define silently
     dropped the use. resolve_typename's leaf lookup required
     `kind == SK_USE` and gave up. Adds a `use_alias` flag to Sym; the
     pass-1 decl scan now marks colliding syms in both directions
     (use-after-type and type-after-use). resolve_typename and the
     N_DOT cexpr branch treat `use_alias` like SK_USE for qualified
     lookup. selfhost check.ww was already lenient on this path so no
     ww-side change was needed; bootstrap fixed point (990-995) holds.
     See cmd/wcc/check.c installdecl pass + N_DOT/resolve_typename and
     cmd/wcc/ww.h Sym.use_alias.

New modules under lib/, each with @test vectors in *_test.ww and wired
into test/wcc/900_stdlib.c (26 modules → all compile):

  - lib/hash/crc64       ECMA, ISO  (mirror of crc32 shape)
  - lib/hash/siphash     SipHash-2-4, buffer-based sum/sum24
  - lib/math/random      SplitMix64 (init, next, u32n, u64n)
  - lib/encoding/base64  RFC 4648 std + url-safe encode/decode + sizes
  - lib/encoding/base32  RFC 4648 std + base32hex encode/decode + sizes

selfhost/cmd/wcc/cgenexpr.ww

@@ -375,10 +375,48 @@ fn cgcast(c: *cgen, n: *node) void = {
 		if (srcstr) { emitline("\tMOVQ\tBX, CX\n"); };
 	};
 	// 0=int, 1=f32, 2=f64. CVT picks one direction per combo;
-	// same-kind casts (int↔int with widening differences,
-	// f64→f64 etc.) stay no-ops at the asm level, matching the
-	// pre-port behaviour for integer casts.
-	if (srcfk == 0 && dstfk == 0) { return; };
+	// int↔int casts narrow via an explicit clamp before the early
+	// return so `(big_u64): u32` doesn't leak the upper 32 bits.
+	// Hare semantics: `expr: T` truncates to T's bit width (mod 2^n).
+	// Mirrors cmd/w6c/cgen.c's N_CAST clamp; signed-narrow targets
+	// (i8/i16/i32) stay no-ops until the assembler grows MOVSBQ /
+	// MOVSWQ / MOVSXD reg-reg forms.
+	if (srcfk == 0 && dstfk == 0) {
+		let tn: *node = n.rhs;
+		// Walk through alias chains (`type random = u64`).
+		for (tn != nil) {
+			if (tn.kind != nkind.N_TNAME) { tn = nil; }
+			else {
+				let nm: str = tn.str;
+				if (primsize(nm) > 0) { break; };
+				let alias: *node = aliaslookup(c, nm);
+				if (alias == nil) { tn = nil; }
+				else { tn = alias; };
+			};
+		};
+		if (tn != nil) {
+			let nm: str = tn.str;
+			let sz: i32 = primsize(nm);
+			let is_unsigned: bool = typenameisunsigned(nm);
+			let is_bool: bool = streq(nm, "bool");
+			if (sz > 0) { if (sz < 8) {
+				if (is_unsigned) {
+					if (sz == 4) {
+						emitline("\tMOVL\tAX, AX\n");
+					} else {
+						let mask: i64 = 0xFFi64;
+						if (sz == 2) { mask = 0xFFFFi64; };
+						emitline("\tANDQ\t$");
+						emitint(mask);
+						emitline(", AX\n");
+					};
+				} else { if (is_bool) {
+					emitline("\tANDQ\t$255, AX\n");
+				}; };
+			}; };
+		};
+		return;
+	};
 	if (srcfk == 0 && dstfk == 2) {
 		emitline("\tCVTSI2SD\tAX, X0\n");
 		return;