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w6c+wcc+selfhost+lib: int-cast truncate + use_alias, 5 new modules

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Two cgen/check bugs surfaced by new lib modules, plus the modules
themselves (crc64, siphash, random, base64, base32).

  1. `(big_u64): u32` (and `: u16`, `: u8`, `: bool`) didn't truncate.
     N_CAST emitted nothing for int↔int; the value stayed in AX with
     its upper bits intact and downstream CMPQ/DIVQ misread the slot.
     The TK_TILDE path already had clamp logic for the same reason —
     N_CAST was the missing case. Both stages now MOVL r,r for u32 and
     ANDQ $mask for u8/u16/bool. Signed-narrow (i8/i16/i32) stays
     no-op until w6a grows reg-reg MOVSBQ/MOVSWQ/MOVSXD. selfhost
     cgcast walks alias chains via aliaslookup before checking
     primsize/typenameisunsigned so `(u: random)` where
     `type random = u64` still bypasses the clamp.
     See cmd/w6c/cgen.c N_CAST and selfhost/cmd/wcc/cgenexpr.ww cgcast.

  2. `mod.mod` type refs (`random.random` when the imported module
     declares `export type random = u64;`) failed with "unknown type".
     The driver concatenates imports into one flat scope, so SK_USE
     `random` collided with SK_TYPE `random` and scope_define silently
     dropped the use. resolve_typename's leaf lookup required
     `kind == SK_USE` and gave up. Adds a `use_alias` flag to Sym; the
     pass-1 decl scan now marks colliding syms in both directions
     (use-after-type and type-after-use). resolve_typename and the
     N_DOT cexpr branch treat `use_alias` like SK_USE for qualified
     lookup. selfhost check.ww was already lenient on this path so no
     ww-side change was needed; bootstrap fixed point (990-995) holds.
     See cmd/wcc/check.c installdecl pass + N_DOT/resolve_typename and
     cmd/wcc/ww.h Sym.use_alias.

New modules under lib/, each with @test vectors in *_test.ww and wired
into test/wcc/900_stdlib.c (26 modules → all compile):

  - lib/hash/crc64       ECMA, ISO  (mirror of crc32 shape)
  - lib/hash/siphash     SipHash-2-4, buffer-based sum/sum24
  - lib/math/random      SplitMix64 (init, next, u32n, u64n)
  - lib/encoding/base64  RFC 4648 std + url-safe encode/decode + sizes
  - lib/encoding/base32  RFC 4648 std + base32hex encode/decode + sizes
This commit is contained in:
Hojun-Cho
2026-05-13 14:58:36 +09:00
parent cbcc0167ae
commit 7a4f60b041
17 changed files with 1302 additions and 23 deletions
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33
cmd/w6c/cgen.c
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@@ -3474,6 +3474,39 @@ cgexpr(Cg *c, Node *n, Local *locals)
ins2(c, A_MOVQ, areg(D_BX), areg(D_CX));
}
}
/* Narrowing integer cast: clamp AX to the target width so
* downstream 64-bit ops see a value within the declared
* range. Hare semantics: `expr: T` truncates to T's bit
* width (mod 2^n). Without this, `(big_u64): u32` left the
* upper 32 bits intact and CMPQ/DIVQ misread the value.
*
* Unsigned targets only here. Signed-narrow targets (i8/
* i16/i32) need MOVSBQ / MOVSWQ / MOVSXD in their reg-reg
* form which the assembler doesn't expose yet; callers
* that need a clean signed-narrow value either keep the
* value in range before the cast (as strconv does with
* an explicit bounds check) or AND the low bits manually.
* Tracking this gap is part of the same TODO. */
if (!from_f && !to_f && n->type) {
Type *tt = n->type;
Type *tu = (tt && tt->kind == TY_NAMED) ? tt->under : tt;
if (tu && type_isint(tu) && tu->size > 0
&& tu->size < 8 && type_isunsigned(tu)) {
if (tu->size == 4) {
ins2(c, A_MOVL, areg(D_AX), areg(D_AX));
} else {
u64 mask = ((u64)1 << (tu->size * 8)) - 1;
ins2(c, A_ANDQ, aimm((i64)mask),
areg(D_AX));
}
}
/* TY_BOOL is size 1 too; clamp to a single byte so
* `(u32_val): bool` produces 0 or a low-byte value
* instead of leaking the upper bits. */
if (tu && tu->kind == TY_BOOL) {
ins2(c, A_ANDQ, aimm(0xFF), areg(D_AX));
}
}
break;
}
case N_DOT: {