From 63332fef50cd7d08e715dfa083887f5c82ecd196 Mon Sep 17 00:00:00 2001 From: Hojun-Cho Date: Sun, 17 May 2026 02:12:29 +0900 Subject: [PATCH] cstage+selfhost+test: sign-aware codegen for signed int div/mod (#16) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Shared miscompile in both stages — not a divergence. Bootstrap byte-id passed throughout because both stages emitted the same wrong asm. Both the C cgen (cmd/w6c/cgen.c TK_SLASH/TK_PERCENT) and the ww cgen (selfhost/cmd/wcc/cgenexpr.ww) prepped IDIVQ with `MOVQ $0, DX`, which is the unsigned 128-bit dividend shape. For a negative RAX, the CPU then divides 2^64 + (-RAX) by the divisor — unsigned wraparound, not signed division. Surfaced via lib/time/add() needing the verbatim Hare signed-%-normalisation in ref/hare/time/arithm.ha. Fix: emit CQO (sign-extend RAX into RDX:RAX, REX.W 99) on the signed arm; keep MOVQ $0, DX on the unsigned arm where the DIVQ-vs-IDIVQ dispatch was already correct. Since both stages always emit 64-bit IDIVQ regardless of source width, a single CQO suffices for i64/i32/i16/i8 — the dividend already lives in RAX sign-extended. No CDQ/CWTL/CBTW needed. Symmetric stages (rule 10): both stages were broken identically; both get the same surgical fix. Adds A_CQO to each assembler's opcode set: cstage in cmd/w6c/6.out.h + cmd/w6c/txt.c + cmd/w6a/{parse,asm}.c; wwstage in selfhost/cmd/w6a/{types,parse,asm}.ww. Class B (shared miscompile) — new in the session's polarity catalog. Bootstrap byte-id is useless for catching it; semantic 9xx runtime tests are the right shape. test/wcc/978_intdiv_signed.c covers 27 rows × 2 drivers = 54 fixtures across {i8,i16,i32,i64,u8,u16,u32,u64} × {/, %} with width-boundary minima (INT8_MIN, INT16_MIN, INT32_MIN, INT64_MIN/2) and high-bit-set unsigned anchors. INT64_MIN is spelled (-INT64_MAX) - 1 per task #17 (wwstage NEGQ-over-imm drops digits on -9223372036854775808i64); that literal-cgen bug is unrelated to this fix. Two known compound-assign workarounds at cmd/w6c/cgen.c:3765 (TK_SLASHEQ IDENT-local) and :3549 (TK_SLASHEQ/TK_PERCENTEQ deref-compound) remain in tree; both depend on the assembler having CQO, so they revert in a follow-up commit citing this one. --- Makefile | 5 + cmd/w6a/asm.c | 5 + cmd/w6a/parse.c | 2 +- cmd/w6c/6.out.h | 3 + cmd/w6c/cgen.c | 15 +- cmd/w6c/txt.c | 4 + selfhost/cmd/w6a/asm.ww | 5 + selfhost/cmd/w6a/main.combined.ww | 11 + selfhost/cmd/w6a/parse.ww | 1 + selfhost/cmd/w6a/types.ww | 5 + selfhost/cmd/w6c/main.combined.ww | 23 +- selfhost/cmd/wcc/cgenexpr.ww | 23 +- selfhost/cmd/wwdump/main.combined.ww | 23 +- test/wcc/978_intdiv_signed.c | 375 +++++++++++++++++++++++++++ 14 files changed, 478 insertions(+), 22 deletions(-) create mode 100644 test/wcc/978_intdiv_signed.c diff --git a/Makefile b/Makefile index 0dd3444d..d0df299b 100644 --- a/Makefile +++ b/Makefile @@ -253,6 +253,7 @@ TESTS = $(BIN)/test_smoke $(BIN)/test_lex $(BIN)/test_parse $(BIN)/test_check \ $(BIN)/test_fmt_run $(BIN)/test_log_run $(BIN)/test_fnmatch_run \ $(BIN)/test_shlex_run $(BIN)/test_getenv_run $(BIN)/test_dirs_run \ $(BIN)/test_stat_run \ + $(BIN)/test_intdiv_signed \ $(BIN)/test_memio_run $(BIN)/test_temp_run $(BIN)/test_getopt_run \ $(BIN)/test_base32_run $(BIN)/test_base64_run \ $(BIN)/test_adler32_run $(BIN)/test_crc16_run \ @@ -584,6 +585,10 @@ $(BIN)/test_stat_run: test/wcc/976_stat_run.c $(BIN)/ww $(BIN)/w6c \ $(BIN)/w6a $(BIN)/w6l $(LIB)/libwwrt.a | $(BIN) $(CC) $(CFLAGS) -o $@ $< +$(BIN)/test_intdiv_signed: test/wcc/978_intdiv_signed.c $(BIN)/ww $(BIN)/w6c \ + $(BIN)/w6a $(BIN)/w6l $(LIB)/libwwrt.a | $(BIN) + $(CC) $(CFLAGS) -o $@ $< + $(BIN)/test_memio_run: test/wcc/980_memio_run.c $(BIN)/ww $(BIN)/w6c \ $(BIN)/w6a $(BIN)/w6l $(LIB)/libwwrt.a | $(BIN) $(CC) $(CFLAGS) -o $@ $< diff --git a/cmd/w6a/asm.c b/cmd/w6a/asm.c index d59c6cb4..e380a9ac 100644 --- a/cmd/w6a/asm.c +++ b/cmd/w6a/asm.c @@ -15,6 +15,7 @@ * IMULQ reg, reg — 0F AF /r (REX.W) * IDIVQ reg — F7 /7 (REX.W) * DIVQ reg — F7 /6 (REX.W) (unsigned) + * CQO — REX.W 99 (sign-extend RAX→RDX:RAX) * NEGQ/NOTQ reg — F7 /3, F7 /2 (REX.W) * SHLQ/SHRQ CL, reg — D3 /4, D3 /5 (REX.W) * CMPQ reg, reg — 39 /r (REX.W) @@ -396,6 +397,10 @@ a_encode(Asm *a) /* unsigned divide; shares the F7 group with IDIVQ but * uses /6 instead of /7. */ encode_unary(a, 0xF7, 6, p->to.type); break; + case A_CQO: + /* REX.W 99 — sign-extend RAX into RDX:RAX. */ + a_emit_byte(a, 0x48); a_emit_byte(a, 0x99); + break; case A_MOVQ: if (p->from.type == D_CONST && p->to.type >= D_AX && p->to.type <= D_R15) { diff --git a/cmd/w6a/parse.c b/cmd/w6a/parse.c index 5b896f6e..ae3e61a5 100644 --- a/cmd/w6a/parse.c +++ b/cmd/w6a/parse.c @@ -103,7 +103,7 @@ opcode_lookup(const char *m) { "CVTSS2SD", A_CVTSS2SD }, { "ADDQ", A_ADDQ }, { "SUBQ", A_SUBQ }, { "IMULQ",A_IMULQ},{ "IDIVQ",A_IDIVQ}, - { "DIVQ", A_DIVQ }, + { "DIVQ", A_DIVQ },{ "CQO", A_CQO }, { "NEGQ", A_NEGQ },{ "NOTQ", A_NOTQ }, { "ANDQ", A_ANDQ },{ "ORQ", A_ORQ }, { "XORQ", A_XORQ }, diff --git a/cmd/w6c/6.out.h b/cmd/w6c/6.out.h index fd0b299e..83a44d16 100644 --- a/cmd/w6c/6.out.h +++ b/cmd/w6c/6.out.h @@ -83,6 +83,9 @@ enum { A_IMULQ, A_IDIVQ, A_DIVQ, /* unsigned 64-bit divide; sibling of IDIVQ */ + A_CQO, /* sign-extend RAX into RDX:RAX; the signed-division + * prep that pairs with IDIVQ (DIVQ pairs with a + * MOVQ $0, DX zero-fill). */ A_NEGQ, A_NOTQ, A_ANDQ, diff --git a/cmd/w6c/cgen.c b/cmd/w6c/cgen.c index b4549169..45b41a32 100644 --- a/cmd/w6c/cgen.c +++ b/cmd/w6c/cgen.c @@ -2166,17 +2166,26 @@ cgexpr(Cg *c, Node *n, Local *locals) /* Use DIV (unsigned) when either operand is an unsigned * integer type — IDIV would sign-extend a u64 with high * bit set into a negative i64 and produce wrong results - * (see strconv.u64tos with v = 1 << 63). */ + * (see strconv.u64tos with v = 1 << 63). Signed IDIV + * needs CQO to sign-extend RAX into RDX:RAX; zeroing + * DX would treat a negative dividend as a huge unsigned + * 128-bit value. */ int unsignd = (n->lhs && type_isunsigned(n->lhs->type)) || (n->rhs && type_isunsigned(n->rhs->type)); - ins2(c, A_MOVQ, aimm(0), areg(D_DX)); + if (unsignd) + ins2(c, A_MOVQ, aimm(0), areg(D_DX)); + else + ins0(c, A_CQO); ins1(c, unsignd ? A_DIVQ : A_IDIVQ, areg(D_BX)); break; } case TK_PERCENT: { int unsignd = (n->lhs && type_isunsigned(n->lhs->type)) || (n->rhs && type_isunsigned(n->rhs->type)); - ins2(c, A_MOVQ, aimm(0), areg(D_DX)); + if (unsignd) + ins2(c, A_MOVQ, aimm(0), areg(D_DX)); + else + ins0(c, A_CQO); ins1(c, unsignd ? A_DIVQ : A_IDIVQ, areg(D_BX)); ins2(c, A_MOVQ, areg(D_DX), areg(D_AX)); break; diff --git a/cmd/w6c/txt.c b/cmd/w6c/txt.c index d33da5d5..3200b866 100644 --- a/cmd/w6c/txt.c +++ b/cmd/w6c/txt.c @@ -61,6 +61,7 @@ anames(int op) case A_IMULQ: return "IMULQ"; case A_IDIVQ: return "IDIVQ"; case A_DIVQ: return "DIVQ"; + case A_CQO: return "CQO"; case A_NEGQ: return "NEGQ"; case A_NOTQ: return "NOTQ"; case A_ANDQ: return "ANDQ"; @@ -164,6 +165,9 @@ txt_emit(FILE *f, Prog *head) case A_SYSCALL: fputs("\tSYSCALL\n", f); break; + case A_CQO: + fputs("\tCQO\n", f); + break; case A_NEGQ: case A_NOTQ: case A_PUSHQ: diff --git a/selfhost/cmd/w6a/asm.ww b/selfhost/cmd/w6a/asm.ww index dbc4bb2e..73a728d4 100644 --- a/selfhost/cmd/w6a/asm.ww +++ b/selfhost/cmd/w6a/asm.ww @@ -357,6 +357,11 @@ export fn encode(a: *asm_) i32 = { if (op == A_NOTQ) { encodeunary(a, 247u8, 2, p.to.atype); p = p.link; continue; }; if (op == A_IDIVQ) { encodeunary(a, 247u8, 7, p.to.atype); p = p.link; continue; }; if (op == A_DIVQ) { encodeunary(a, 247u8, 6, p.to.atype); p = p.link; continue; }; + if (op == A_CQO) { + emitbyte(a, 72u8); // REX.W (0x48) + emitbyte(a, 153u8); // 0x99 + p = p.link; continue; + }; if (op == A_MOVQ) { let ft: i32 = p.from.atype; diff --git a/selfhost/cmd/w6a/main.combined.ww b/selfhost/cmd/w6a/main.combined.ww index 2e7432a6..168edeb0 100644 --- a/selfhost/cmd/w6a/main.combined.ww +++ b/selfhost/cmd/w6a/main.combined.ww @@ -904,6 +904,11 @@ def A_SYSCALL: i32 = 59; def A_DATAW: i32 = 60; def A_DATAR: i32 = 61; +// REX.W 99 — sign-extend RAX into RDX:RAX. Pairs with IDIVQ for +// signed division; pendant to the MOVQ $0, DX zero-fill that pairs +// with DIVQ. +def A_CQO: i32 = 66; + // ---- structs (mirror cmd/w6a/a.h) -------------------------------------- type aoperand = struct { @@ -1116,6 +1121,7 @@ fn opcodelookup(p: *u8, n: u64) i32 = { if (streqlit(p, n, "IMULQ")) { return A_IMULQ; }; if (streqlit(p, n, "IDIVQ")) { return A_IDIVQ; }; if (streqlit(p, n, "DIVQ")) { return A_DIVQ; }; + if (streqlit(p, n, "CQO")) { return A_CQO; }; if (streqlit(p, n, "NEGQ")) { return A_NEGQ; }; if (streqlit(p, n, "NOTQ")) { return A_NOTQ; }; if (streqlit(p, n, "ANDQ")) { return A_ANDQ; }; @@ -2003,6 +2009,11 @@ export fn encode(a: *asm_) i32 = { if (op == A_NOTQ) { encodeunary(a, 247u8, 2, p.to.atype); p = p.link; continue; }; if (op == A_IDIVQ) { encodeunary(a, 247u8, 7, p.to.atype); p = p.link; continue; }; if (op == A_DIVQ) { encodeunary(a, 247u8, 6, p.to.atype); p = p.link; continue; }; + if (op == A_CQO) { + emitbyte(a, 72u8); // REX.W (0x48) + emitbyte(a, 153u8); // 0x99 + p = p.link; continue; + }; if (op == A_MOVQ) { let ft: i32 = p.from.atype; diff --git a/selfhost/cmd/w6a/parse.ww b/selfhost/cmd/w6a/parse.ww index 25c7c4d2..89a40c7a 100644 --- a/selfhost/cmd/w6a/parse.ww +++ b/selfhost/cmd/w6a/parse.ww @@ -61,6 +61,7 @@ fn opcodelookup(p: *u8, n: u64) i32 = { if (streqlit(p, n, "IMULQ")) { return A_IMULQ; }; if (streqlit(p, n, "IDIVQ")) { return A_IDIVQ; }; if (streqlit(p, n, "DIVQ")) { return A_DIVQ; }; + if (streqlit(p, n, "CQO")) { return A_CQO; }; if (streqlit(p, n, "NEGQ")) { return A_NEGQ; }; if (streqlit(p, n, "NOTQ")) { return A_NOTQ; }; if (streqlit(p, n, "ANDQ")) { return A_ANDQ; }; diff --git a/selfhost/cmd/w6a/types.ww b/selfhost/cmd/w6a/types.ww index dce8e79b..9b392fc1 100644 --- a/selfhost/cmd/w6a/types.ww +++ b/selfhost/cmd/w6a/types.ww @@ -132,6 +132,11 @@ def A_SYSCALL: i32 = 59; def A_DATAW: i32 = 60; def A_DATAR: i32 = 61; +// REX.W 99 — sign-extend RAX into RDX:RAX. Pairs with IDIVQ for +// signed division; pendant to the MOVQ $0, DX zero-fill that pairs +// with DIVQ. +def A_CQO: i32 = 66; + // ---- structs (mirror cmd/w6a/a.h) -------------------------------------- type aoperand = struct { diff --git a/selfhost/cmd/w6c/main.combined.ww b/selfhost/cmd/w6c/main.combined.ww index 860249a0..32c2e414 100644 --- a/selfhost/cmd/w6c/main.combined.ww +++ b/selfhost/cmd/w6c/main.combined.ww @@ -12353,15 +12353,26 @@ fn cgbin(c: *cgen, n: *node) void = { if (n.op == tkind.TK_MINUS) { emitline("\tSUBQ\tBX, AX\n"); return; }; if (n.op == tkind.TK_STAR) { emitline("\tIMULQ\tBX, AX\n"); return; }; if (n.op == tkind.TK_SLASH) { - emitline("\tMOVQ\t$0, DX\n"); - if (unsignd) { emitline("\tDIVQ\tBX\n"); } - else { emitline("\tIDIVQ\tBX\n"); }; + // Signed IDIV reads dividend from RDX:RAX; CQO sign-extends + // RAX. Zero-filling DX would treat a negative RAX as a huge + // positive 128-bit value. Unsigned DIV needs RDX zero. + if (unsignd) { + emitline("\tMOVQ\t$0, DX\n"); + emitline("\tDIVQ\tBX\n"); + } else { + emitline("\tCQO\n"); + emitline("\tIDIVQ\tBX\n"); + }; return; }; if (n.op == tkind.TK_PERCENT) { - emitline("\tMOVQ\t$0, DX\n"); - if (unsignd) { emitline("\tDIVQ\tBX\n"); } - else { emitline("\tIDIVQ\tBX\n"); }; + if (unsignd) { + emitline("\tMOVQ\t$0, DX\n"); + emitline("\tDIVQ\tBX\n"); + } else { + emitline("\tCQO\n"); + emitline("\tIDIVQ\tBX\n"); + }; emitline("\tMOVQ\tDX, AX\n"); return; }; diff --git a/selfhost/cmd/wcc/cgenexpr.ww b/selfhost/cmd/wcc/cgenexpr.ww index d9012c2e..5f44a073 100644 --- a/selfhost/cmd/wcc/cgenexpr.ww +++ b/selfhost/cmd/wcc/cgenexpr.ww @@ -2536,15 +2536,26 @@ fn cgbin(c: *cgen, n: *node) void = { if (n.op == tkind.TK_MINUS) { emitline("\tSUBQ\tBX, AX\n"); return; }; if (n.op == tkind.TK_STAR) { emitline("\tIMULQ\tBX, AX\n"); return; }; if (n.op == tkind.TK_SLASH) { - emitline("\tMOVQ\t$0, DX\n"); - if (unsignd) { emitline("\tDIVQ\tBX\n"); } - else { emitline("\tIDIVQ\tBX\n"); }; + // Signed IDIV reads dividend from RDX:RAX; CQO sign-extends + // RAX. Zero-filling DX would treat a negative RAX as a huge + // positive 128-bit value. Unsigned DIV needs RDX zero. + if (unsignd) { + emitline("\tMOVQ\t$0, DX\n"); + emitline("\tDIVQ\tBX\n"); + } else { + emitline("\tCQO\n"); + emitline("\tIDIVQ\tBX\n"); + }; return; }; if (n.op == tkind.TK_PERCENT) { - emitline("\tMOVQ\t$0, DX\n"); - if (unsignd) { emitline("\tDIVQ\tBX\n"); } - else { emitline("\tIDIVQ\tBX\n"); }; + if (unsignd) { + emitline("\tMOVQ\t$0, DX\n"); + emitline("\tDIVQ\tBX\n"); + } else { + emitline("\tCQO\n"); + emitline("\tIDIVQ\tBX\n"); + }; emitline("\tMOVQ\tDX, AX\n"); return; }; diff --git a/selfhost/cmd/wwdump/main.combined.ww b/selfhost/cmd/wwdump/main.combined.ww index 22fa5040..19d628e3 100644 --- a/selfhost/cmd/wwdump/main.combined.ww +++ b/selfhost/cmd/wwdump/main.combined.ww @@ -12353,15 +12353,26 @@ fn cgbin(c: *cgen, n: *node) void = { if (n.op == tkind.TK_MINUS) { emitline("\tSUBQ\tBX, AX\n"); return; }; if (n.op == tkind.TK_STAR) { emitline("\tIMULQ\tBX, AX\n"); return; }; if (n.op == tkind.TK_SLASH) { - emitline("\tMOVQ\t$0, DX\n"); - if (unsignd) { emitline("\tDIVQ\tBX\n"); } - else { emitline("\tIDIVQ\tBX\n"); }; + // Signed IDIV reads dividend from RDX:RAX; CQO sign-extends + // RAX. Zero-filling DX would treat a negative RAX as a huge + // positive 128-bit value. Unsigned DIV needs RDX zero. + if (unsignd) { + emitline("\tMOVQ\t$0, DX\n"); + emitline("\tDIVQ\tBX\n"); + } else { + emitline("\tCQO\n"); + emitline("\tIDIVQ\tBX\n"); + }; return; }; if (n.op == tkind.TK_PERCENT) { - emitline("\tMOVQ\t$0, DX\n"); - if (unsignd) { emitline("\tDIVQ\tBX\n"); } - else { emitline("\tIDIVQ\tBX\n"); }; + if (unsignd) { + emitline("\tMOVQ\t$0, DX\n"); + emitline("\tDIVQ\tBX\n"); + } else { + emitline("\tCQO\n"); + emitline("\tIDIVQ\tBX\n"); + }; emitline("\tMOVQ\tDX, AX\n"); return; }; diff --git a/test/wcc/978_intdiv_signed.c b/test/wcc/978_intdiv_signed.c new file mode 100644 index 00000000..e0ac55d2 --- /dev/null +++ b/test/wcc/978_intdiv_signed.c @@ -0,0 +1,375 @@ +/* + * 978_intdiv_signed — runtime semantics of integer `/` and `%` across + * the {i8,i16,i32,i64,u8,u16,u32,u64} × {/, %} matrix, plus the + * width-boundary minima. + * + * Class B (shared miscompile, not divergence): both cstage and + * wwstage previously emitted `MOVQ $0, DX + IDIVQ` on the signed + * arm, treating a negative dividend as a huge unsigned 128-bit + * value. Bootstrap byte-id passed throughout — both stages stomped + * the same way — so only a semantic runtime test catches it. The + * fix swaps the prep to `CQO` (sign-extend RAX into RDX:RAX) on + * the signed arm of TK_SLASH/TK_PERCENT; unsigned stays MOVQ-zero + + * DIVQ. See cmd/w6c/cgen.c TK_SLASH/TK_PERCENT and the matching + * selfhost/cmd/wcc/cgenexpr.ww branches. + * + * Unsigned rows pin the DIVQ arm against future regression — the + * cgen.c comment from #41 (high-bit-set u64 / 2) is exactly the + * shape that the unsigned-vs-signed dispatch protects. + * + * Same dual-driver runner as 640_int_cast_signed.c: each row gets + * compiled by both cstage `ww` and wwstage `ww_ww` (when built), + * with the binary exit code carrying the per-case verdict (42 = ok). + */ +#include +#include +#include +#include +#include +#include + +static int +runwait(const char *cmd) +{ + int rc = system(cmd); + if (rc == -1) return -1; + if (WIFEXITED(rc)) return WEXITSTATUS(rc); + return -1; +} + +struct row { const char *label; const char *src; int want; }; + +static const struct row rows[] = { + /* ---- i64 signed: negative dividend, positive divisor ---------- */ + { "i64_div_neg_dividend", + "fn main() i32 = {\n" + " let a: i64 = -100i64;\n" + " let b: i64 = 1000000000i64;\n" + " if (a / b == 0i64) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + { "i64_mod_neg_dividend", + "fn main() i32 = {\n" + " let a: i64 = -100i64;\n" + " let b: i64 = 1000000000i64;\n" + " if (a % b == -100i64) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + /* ---- i64 signed: positive dividend, negative divisor ---------- */ + { "i64_div_neg_divisor", + "fn main() i32 = {\n" + " let a: i64 = 50i64;\n" + " let b: i64 = -3i64;\n" + " if (a / b == -16i64) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + { "i64_mod_neg_divisor", + "fn main() i32 = {\n" + " let a: i64 = 50i64;\n" + " let b: i64 = -3i64;\n" + " if (a % b == 2i64) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + /* ---- i64 signed: both negative -------------------------------- */ + { "i64_div_both_negative", + "fn main() i32 = {\n" + " let a: i64 = -50i64;\n" + " let b: i64 = -3i64;\n" + " if (a / b == 16i64) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + { "i64_mod_both_negative", + "fn main() i32 = {\n" + " let a: i64 = -50i64;\n" + " let b: i64 = -3i64;\n" + " if (a % b == -2i64) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + /* ---- i64 signed: both positive (sanity / regression anchor) --- */ + { "i64_div_both_positive", + "fn main() i32 = {\n" + " let a: i64 = 50i64;\n" + " let b: i64 = 3i64;\n" + " if (a / b == 16i64) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + { "i64_mod_both_positive", + "fn main() i32 = {\n" + " let a: i64 = 50i64;\n" + " let b: i64 = 3i64;\n" + " if (a % b == 2i64) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + /* ---- i64 boundary: INT64_MIN ---------------------------------- * + * INT64_MIN / -1 would SIGFPE (signed overflow); /2 instead. + * The literal `-9223372036854775808i64` triggers task #17 + * (wwstage NEGQ-over-imm drops digits → `MOVQ $-, AX`), so + * we spell it `(-INT64_MAX) - 1` to sidestep that orthogonal + * bug until #17 lands. */ + { "i64_div_INT64_MIN_by_two", + "fn main() i32 = {\n" + " let a: i64 = (-9223372036854775807i64) - 1i64;\n" + " let b: i64 = 2i64;\n" + " if (a / b == -4611686018427387904i64) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + { "i64_mod_INT64_MIN_by_two", + "fn main() i32 = {\n" + " let a: i64 = (-9223372036854775807i64) - 1i64;\n" + " let b: i64 = 2i64;\n" + " if (a % b == 0i64) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + + /* ---- i32 signed ----------------------------------------------- */ + { "i32_div_neg_dividend", + "fn main() i32 = {\n" + " let x: i32 = -100i32;\n" + " let y: i32 = 7i32;\n" + " if (x / y == -14i32) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + { "i32_mod_neg_dividend", + "fn main() i32 = {\n" + " let x: i32 = -100i32;\n" + " let y: i32 = 7i32;\n" + " if (x % y == -2i32) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + { "i32_div_INT32_MIN_by_two", + "fn main() i32 = {\n" + " let x: i32 = -2147483648i32;\n" + " let y: i32 = 2i32;\n" + " if (x / y == -1073741824i32) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + { "i32_mod_INT32_MIN_by_two", + "fn main() i32 = {\n" + " let x: i32 = -2147483648i32;\n" + " let y: i32 = 2i32;\n" + " if (x % y == 0i32) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + + /* ---- i16 signed ----------------------------------------------- */ + { "i16_div_neg_dividend", + "fn main() i32 = {\n" + " let a: i16 = -100i16;\n" + " let b: i16 = 7i16;\n" + " if (a / b == -14i16) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + { "i16_mod_neg_dividend", + "fn main() i32 = {\n" + " let a: i16 = -100i16;\n" + " let b: i16 = 7i16;\n" + " if (a % b == -2i16) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + { "i16_div_INT16_MIN_by_two", + "fn main() i32 = {\n" + " let a: i16 = -32768i16;\n" + " let b: i16 = 2i16;\n" + " if (a / b == -16384i16) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + + /* ---- i8 signed ------------------------------------------------ */ + { "i8_div_neg_dividend", + "fn main() i32 = {\n" + " let a: i8 = -100i8;\n" + " let b: i8 = 7i8;\n" + " if (a / b == -14i8) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + { "i8_mod_neg_dividend", + "fn main() i32 = {\n" + " let a: i8 = -100i8;\n" + " let b: i8 = 7i8;\n" + " if (a % b == -2i8) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + { "i8_div_INT8_MIN_by_two", + "fn main() i32 = {\n" + " let a: i8 = -128i8;\n" + " let b: i8 = 2i8;\n" + " if (a / b == -64i8) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + + /* ---- u64 unsigned: high-bit-set / 2 must not sign-extend ----- */ + { "u64_div_high_bit_set", + "fn main() i32 = {\n" + " let a: u64 = 0x8000000000000001u64;\n" + " let b: u64 = 2u64;\n" + " if (a / b == 0x4000000000000000u64) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + { "u64_mod_high_bit_set", + "fn main() i32 = {\n" + " let a: u64 = 0x8000000000000001u64;\n" + " let b: u64 = 2u64;\n" + " if (a % b == 1u64) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + + /* ---- u32 unsigned: high-bit-set / 2 -------------------------- */ + { "u32_div_high_bit_set", + "fn main() i32 = {\n" + " let a: u32 = 0x80000001u32;\n" + " let b: u32 = 2u32;\n" + " if (a / b == 0x40000000u32) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + { "u32_mod_high_bit_set", + "fn main() i32 = {\n" + " let a: u32 = 0x80000001u32;\n" + " let b: u32 = 2u32;\n" + " if (a % b == 1u32) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + + /* ---- u16 unsigned: high-bit-set / 2 -------------------------- */ + { "u16_div_high_bit_set", + "fn main() i32 = {\n" + " let a: u16 = 0xFFFFu16;\n" + " let b: u16 = 2u16;\n" + " if (a / b == 0x7FFFu16) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + + /* ---- u8 unsigned: high-bit-set / 2 --------------------------- */ + { "u8_div_high_bit_set", + "fn main() i32 = {\n" + " let a: u8 = 0xFFu8;\n" + " let b: u8 = 2u8;\n" + " if (a / b == 0x7Fu8) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, + + /* ---- mixed-type-flag row: i64 cast to u64 forces unsigned arm. + * `unsignd` flag fires if either operand is unsigned — pin it. */ + { "mixed_unsigned_rhs_picks_unsigned", + "fn main() i32 = {\n" + " let a: i64 = 100i64;\n" + " let b: u64 = 7u64;\n" + " if ((a: u64) / b == 14u64) { return 42; };\n" + " return 0;\n" + "};\n", + 42 }, +}; + +static int +run_driver(const char *driver, const struct row *r, int i) +{ + char src[64], tmpdir[64], cmd[1024]; + snprintf(src, sizeof src, "/tmp/wwid_%d_%d.ww", getpid(), i); + snprintf(tmpdir, sizeof tmpdir, "/tmp/wwid_%d_d_%d", getpid(), i); + + FILE *f = fopen(src, "wb"); + if (!f) return -1; + fputs(r->src, f); + fclose(f); + + mkdir(tmpdir, 0755); + snprintf(cmd, sizeof cmd, "cd %s && %s build %s", + tmpdir, driver, src); + if (runwait(cmd) != 0) { + fprintf(stderr, "row[%s]: build via %s failed\n", + r->label, driver); + unlink(src); rmdir(tmpdir); + return -1; + } + + const char *base = strrchr(src, '/'); + base = base ? base + 1 : src; + char outbin[128]; + snprintf(outbin, sizeof outbin, "%s/%s", tmpdir, base); + char *dot = strrchr(outbin, '.'); + if (dot && strcmp(dot, ".ww") == 0) *dot = '\0'; + int got = runwait(outbin); + + unlink(src); unlink(outbin); rmdir(tmpdir); + return got; +} + +int +main(void) +{ + const char *bin = getenv("BIN"); + if (!bin) bin = "out/bin"; + char absbin[1024]; + if (bin[0] != '/') { + char cwd[1024]; + if (getcwd(cwd, sizeof cwd) == NULL) return 1; + snprintf(absbin, sizeof absbin, "%s/%s", cwd, bin); + bin = absbin; + } + + char cdrv[1024]; + snprintf(cdrv, sizeof cdrv, "%s/ww", bin); + char wdrv[1024]; + snprintf(wdrv, sizeof wdrv, "%s/ww_ww", bin); + + struct { const char *name; const char *path; int gated_on_existence; } + drivers[] = { + { "cstage", cdrv, 0 }, + { "wwstage", wdrv, 1 }, + { NULL, NULL, 0 }, + }; + + int n = (int)(sizeof rows / sizeof rows[0]); + int total = 0, fail = 0; + for (int d = 0; drivers[d].name; d++) { + if (drivers[d].gated_on_existence + && access(drivers[d].path, X_OK) != 0) { + fprintf(stderr, "intdiv_signed: skip %s (no %s)\n", + drivers[d].name, drivers[d].path); + continue; + } + for (int i = 0; i < n; i++) { + int got = run_driver(drivers[d].path, &rows[i], i); + total++; + if (got != rows[i].want) { + fprintf(stderr, + "intdiv_signed[%s][%s]: exit=%d want=%d\n", + drivers[d].name, rows[i].label, + got, rows[i].want); + fail++; + } + } + } + if (fail) { + fprintf(stderr, + "intdiv_signed: %d/%d fixtures failed\n", fail, total); + return 1; + } + printf("intdiv_signed: %d/%d ok\n", total, total); + return 0; +}