cstage+test: walk fields for sret callee struct-copy width (#33)

Callee N_IDENT word-copy loop was driven off slot-padded rt->size;
trailing narrow field (e.g. bool@32 in 33B/40B struct) widened to
MOVQ at the loop tail, diverging from wwstage's natural-size MOVB.
Class A cgen divergence. 9th unmask of session 5, corpus-coverage-
blind on the cstage side — no in-tree lib struct had a narrow
(bool/u8/i8/i16) trailing field until lib/strings.iterator landed
`reverse: bool` per Hare's ref/hare/strings/iter.ha:8.

Pre-fix: cstage cgreturn's sret arm (cgen.c) used `int sz =
(int)rt->size` for its chained `while (k+8<=sz)` MOVQ-MOVL-MOVW-MOVB
copy loop. rt->size is slot-padded (8-rounded for downstream
frame alloc), e.g. 40B for {i32, []u8, bool}. Loop emitted MOVQ
at offset 32 covering the 1-byte bool tail plus 7 bytes of
padding into the caller's sret slot — clobbering the next 7 bytes
of caller frame on read-side. Wwstage's mirror loop drives off
sretretsize → structnaturalsize → max(foff+fsz) = 33B, so it
correctly stops at offset 32 and emits MOVB.

Polarity catalog: cstage OVER-WIDE — slot-padded size driving the
field-copy width. Convergence cstage → wwstage's structnaturalsize
discipline (rule 10 inverse: leaner-correct side wins).

Fix: compute natural size locally in the N_IDENT/N_STRUCTLIT sret
arm via walk over `rt->fields` (max foff+fsz), mirroring wwstage's
`structnaturalsize` (cgenutil.ww:1377). Frame allocation and
`cg_sret_retsize` (used for the caller-side @sretscr slot)
intentionally keep using rt->size — caller scratch sizing is
separate from callee per-field copy width.

Surfaced by lib/strings commit-2 (#30) iterator pre-flight when
the Hare-faithful `reverse: bool` field tripped the cstage-only
mis-width on 993/995 byte-id (strconv → strings → wwdump_ww +
w6c_ww). lib/strings c2 was stashed to land cleanly after this fix.

Note (out-of-scope): the chained MOV loop has no MOVW arm in
either stage, so a trailing i16 emits 2× MOVB at consecutive
offsets. Worth a future cleanup; both stages agree today.

Tests:
  - 730_sret_narrow_field pins narrow-MOV store + load width and
    no-MOVQ@trailing-offset assertions for bool / u8 / i16 / i32
    trailing fields in a 33B-natural struct. 4 rows × 5 sentinels
    = 20 fixtures. cmp -s cstage vs wwstage byte-id per row.
  - 930_sret_narrow_field_run runtime-pins bool true/false, u8
    high-bit, i16 negative, i32 negative, mixed (bool+i32+i64 after
    slice) — 6 scenarios × 2 stages = 12 rows.

104/104 ok. 995_self_rebuild stays green (ww2==ww3==ww4 byte-id).

cmd/w6c/cgen.c

@@ -6611,7 +6611,20 @@ cgstmt(Cg *c, Node *n, Local **locals, int *frame)
 			    && (int)rt->size > 24
 			    && (n->lhs->kind == N_IDENT
 			    || n->lhs->kind == N_STRUCTLIT)) {
-				int sz = (int)rt->size;
+				/* Natural size = max(foff + fsz) over declared
+				 * fields; mirrors selfhost cgenutil.ww
+				 * structnaturalsize / sretretsize. Pre-fix this
+				 * used the slot-padded rt->size, so a trailing
+				 * narrow field (e.g. bool@32 in a 33B struct
+				 * padded to 40B) widened to an 8B MOVQ at the
+				 * loop tail — diverged from wwstage's MOVB
+				 * tail. Task #33, Class A. */
+				int sz = 0;
+				for (Tfield *fl = rt->fields; fl; fl = fl->next) {
+					int end = (int)fl->offset + (int)(fl->type
+					    ? fl->type->size : 8);
+					if (end > sz) sz = end;
+				}
 				if (n->lhs->kind == N_STRUCTLIT) {
 					/* Delegate to the shared *-relative
 					 * fill helper. Same store sequence the