test: port the live cs/ww divergence pins to ww; retire 826 + 944 slim carriers

826_alias_tuple_coerce, 944_alias_accept_run and
944_variant_chain_b95_run all reduced to the same irreducible shape: a
LIVE per-stage asymmetry (probed at HEAD) no symmetric fixture or
@test can host. Ported under the DIVERGE discipline — both sides
asserted loud (826 neg_0: cstage "not assignable to declared pair"
vs wwstage over-accept; #96: cstage runs vs w6c_ww "unsupported
address-of shape"; #277: cstage runs vs ww_ww "deferred #277"), so
a fix on either side fails the row and demands graduation. Owned legs
cited, not duplicated: r826_alias_tuple_* byte rows ride
test-data-byteid, 826's neg_1 went symmetric at HEAD and moves to a
//ww:error fixture per the audit split, the 944 value/reject corpora
live in test/lang/{alias_accept,variant_chain_b95}_test.ww and the
alias_*/vchain_* fixtures. Bundled: one file, one concern (held
divergence pins).
This commit is contained in:
2026-08-08 15:03:20 +09:00
parent a82cfaa6ab
commit 05a5830805
5 changed files with 194 additions and 497 deletions

View File

@@ -408,7 +408,7 @@ OBJECT_WW_TARGETS = $(OBJECT_WW_TESTS:%=wwtest/%)
# cstage-only rejects). Compiler/driver gates like test/sep: they run
# under test-compiler.
MISC_WW_TESTS = test/misc/arrglob_test.ww test/misc/packedwwi_test.ww \
test/misc/reject_test.ww
test/misc/reject_test.ww test/misc/heldasym_test.ww
MISC_WW_TARGETS = $(MISC_WW_TESTS:%=wwtest/%)
BOOTSTRAP_WRAPPER_SOURCES = test/wcc/950_selfcheck.c \
test/wcc/991_w6a_ww.c \